From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:46917) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn2X-0005b3-Rs for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:48:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qtn2W-0006gF-6q for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:48:41 -0400 Received: from mail-yi0-f45.google.com ([209.85.218.45]:33471) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn2W-0006bk-0L for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:48:40 -0400 Received: by mail-yi0-f45.google.com with SMTP id 10so1231438yih.4 for ; Wed, 17 Aug 2011 13:48:39 -0700 (PDT) From: Bryce Lanham Date: Wed, 17 Aug 2011 15:46:20 -0500 Message-Id: <1313614076-28878-16-git-send-email-blanham@gmail.com> In-Reply-To: <1313614076-28878-1-git-send-email-blanham@gmail.com> References: <1313614076-28878-1-git-send-email-blanham@gmail.com> Subject: [Qemu-devel] [PATCH 015/111] m68k: modify movem instruction to manage word List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Andreas Schwab , Laurent Vivier From: Laurent Vivier This patch modifies "movem" to manage "word" and "long" register size instead of only "word". Attach it to M68000 feature. Signed-off-by: Andreas Schwab Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 52 +++++++++++++++++++++++++++++++++------------- 1 files changed, 37 insertions(+), 15 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index e0edc6d..0f9b4eb 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -1173,6 +1173,8 @@ DISAS_INSN(movem) TCGv reg; TCGv tmp; int is_load; + int opsize; + int32_t incr; mask = lduw_code(s->pc); s->pc += 2; @@ -1184,21 +1186,40 @@ DISAS_INSN(movem) addr = tcg_temp_new(); tcg_gen_mov_i32(addr, tmp); is_load = ((insn & 0x0400) != 0); - for (i = 0; i < 16; i++, mask >>= 1) { - if (mask & 1) { - if (i < 8) - reg = DREG(i, 0); - else - reg = AREG(i, 0); - if (is_load) { - tmp = gen_load(s, OS_LONG, addr, 0); - tcg_gen_mov_i32(reg, tmp); - } else { - gen_store(s, OS_LONG, addr, reg); - } - if (mask != 1) - tcg_gen_addi_i32(addr, addr, 4); - } + opsize = (insn & 0x40) != 0 ? OS_LONG : OS_WORD; + incr = opsize_bytes(opsize); + if (!is_load && (insn & 070) == 040) { + for (i = 15; i >= 0; i--, mask >>= 1) { + if (mask & 1) { + if (i < 8) + reg = DREG(i, 0); + else + reg = AREG(i, 0); + gen_store(s, opsize, addr, reg); + if (mask != 1) + tcg_gen_subi_i32(addr, addr, incr); + } + } + tcg_gen_mov_i32(AREG(insn, 0), addr); + } else { + for (i = 0; i < 16; i++, mask >>= 1) { + if (mask & 1) { + if (i < 8) + reg = DREG(i, 0); + else + reg = AREG(i, 0); + if (is_load) { + tmp = gen_load(s, opsize, addr, 1); + tcg_gen_mov_i32(reg, tmp); + } else { + gen_store(s, opsize, addr, reg); + } + if (mask != 1 || (insn & 070) == 030) + tcg_gen_addi_i32(addr, addr, incr); + } + } + if ((insn & 070) == 030) + tcg_gen_mov_i32(AREG(insn, 0), addr); } } @@ -2972,6 +2993,7 @@ void register_m68k_insns (CPUM68KState *env) INSN(swap, 4840, fff8, CF_ISA_A); INSN(swap, 4840, fff8, M68000); INSN(movem, 48c0, fbc0, CF_ISA_A); + INSN(movem, 48c0, fbc0, M68000); INSN(ext, 4880, fff8, CF_ISA_A); INSN(ext, 4880, fff8, M68000); INSN(ext, 48c0, fff8, CF_ISA_A); -- 1.7.2.3