From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:47337) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn3W-00080K-NP for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:49:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qtn3R-0006q4-VL for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:49:42 -0400 Received: from mail-gx0-f173.google.com ([209.85.161.173]:54665) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn3R-0006nC-SK for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:49:37 -0400 Received: by gxk26 with SMTP id 26so1231167gxk.4 for ; Wed, 17 Aug 2011 13:49:22 -0700 (PDT) From: Bryce Lanham Date: Wed, 17 Aug 2011 15:46:43 -0500 Message-Id: <1313614076-28878-39-git-send-email-blanham@gmail.com> In-Reply-To: <1313614076-28878-1-git-send-email-blanham@gmail.com> References: <1313614076-28878-1-git-send-email-blanham@gmail.com> Subject: [Qemu-devel] [PATCH 038/111] m68k: add EA support for negx List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Laurent Vivier From: Laurent Vivier Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 15 ++++++++++----- 1 files changed, 10 insertions(+), 5 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index f2bdef0..ab2073a 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -1483,11 +1483,16 @@ DISAS_INSN(move) DISAS_INSN(negx) { - TCGv reg; + TCGv src; + TCGv dest; + TCGv addr; + int opsize; - gen_flush_flags(s); - reg = DREG(insn, 0); - gen_helper_subx_cc(reg, cpu_env, tcg_const_i32(0), reg); + opsize = insn_opsize(insn, 6); + SRC_EA(src, opsize, -1, &addr); + dest = tcg_temp_new(); + gen_helper_subx_cc(dest, cpu_env, tcg_const_i32(0), src); + DEST_EA(insn, opsize, dest, &addr); } DISAS_INSN(lea) @@ -3780,7 +3785,7 @@ void register_m68k_insns (CPUM68KState *env) INSN(move, 3000, f000, M68000); INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC); INSN(negx, 4080, fff8, CF_ISA_A); - INSN(negx, 4080, fff8, M68000); + INSN(negx, 4000, ff00, M68000); INSN(undef, 40c0, ffc0, M68000); INSN(move_from_sr, 40c0, fff8, CF_ISA_A); INSN(move_from_sr, 40c0, fff8, M68000); -- 1.7.2.3