qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Bryce Lanham <blanham@gmail.com>
To: qemu-devel@nongnu.org
Cc: Laurent Vivier <laurent@vivier.eu>
Subject: [Qemu-devel] [PATCH 047/111] m68k: use read_imm1() when it is possible
Date: Wed, 17 Aug 2011 15:46:52 -0500	[thread overview]
Message-ID: <1313614076-28878-48-git-send-email-blanham@gmail.com> (raw)
In-Reply-To: <1313614076-28878-1-git-send-email-blanham@gmail.com>

From: Laurent Vivier <laurent@vivier.eu>

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/translate.c |   48 +++++++++++++++-------------------------------
 1 files changed, 16 insertions(+), 32 deletions(-)

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 37ee841..f5e56bc 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -567,8 +567,7 @@ static TCGv gen_lea(DisasContext *s, uint16_t insn, int opsize)
     case 5: /* Indirect displacement.  */
         reg = AREG(insn, 0);
         tmp = tcg_temp_new();
-        ext = lduw_code(s->pc);
-        s->pc += 2;
+        ext = read_im16(s);
         tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
         return tmp;
     case 6: /* Indirect index + displacement.  */
@@ -1276,8 +1275,7 @@ DISAS_INSN(movem)
     int opsize;
     int32_t incr;
 
-    mask = lduw_code(s->pc);
-    s->pc += 2;
+    mask = read_im16(s);
     tmp = gen_lea(s, insn, OS_LONG);
     if (IS_NULL_QREG(tmp)) {
         gen_addr_fault(s);
@@ -1339,8 +1337,7 @@ DISAS_INSN(bitop_im)
         opsize = OS_LONG;
     op = (insn >> 6) & 3;
 
-    bitnum = lduw_code(s->pc);
-    s->pc += 2;
+    bitnum = read_im16(s);
     if (bitnum & 0xff00) {
         disas_undef(s, insn);
         return;
@@ -1484,8 +1481,7 @@ DISAS_INSN(cas)
         abort();
     }
 
-    ext = lduw_code(s->pc);
-    s->pc += 2;
+    ext = read_im16(s);
     taddr = gen_lea(s, insn, opsize);
     if (IS_NULL_QREG(taddr)) {
         gen_addr_fault(s);
@@ -1677,8 +1673,7 @@ static void gen_set_sr(DisasContext *s, uint16_t insn, int ccr_only)
     else if ((insn & 0x3f) == 0x3c)
       {
         uint16_t val;
-        val = lduw_code(s->pc);
-        s->pc += 2;
+        val = read_im16(s);
         gen_set_sr_im(s, val, ccr_only);
       }
     else
@@ -1796,8 +1791,7 @@ DISAS_INSN(mull)
 
     /* The upper 32 bits of the product are discarded, so
        muls.l and mulu.l are functionally equivalent.  */
-    ext = lduw_code(s->pc);
-    s->pc += 2;
+    ext = read_im16(s);
     if (ext & 0x400) {
        if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
            gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
@@ -2731,8 +2725,7 @@ DISAS_INSN(bitfield_reg)
 
     reg = DREG(insn, 0);
     op = (insn >> 8) & 7;
-    ext = lduw_code(s->pc);
-    s->pc += 2;
+    ext = read_im16(s);
 
     bitfield_param(ext, &offset, &width, &mask);
 
@@ -2905,8 +2898,7 @@ DISAS_INSN(bitfield_mem)
     TCGv tmp;
 
     op = (insn >> 8) & 7;
-    ext = lduw_code(s->pc);
-    s->pc += 2;
+    ext = read_im16(s);
     src = gen_lea(s, insn, OS_LONG);
     if (IS_NULL_QREG(src)) {
        gen_addr_fault(s);
@@ -3010,14 +3002,12 @@ DISAS_INSN(strldsr)
     uint32_t addr;
 
     addr = s->pc - 2;
-    ext = lduw_code(s->pc);
-    s->pc += 2;
+    ext = read_im16(s);
     if (ext != 0x46FC) {
         gen_exception(s, addr, EXCP_UNSUPPORTED);
         return;
     }
-    ext = lduw_code(s->pc);
-    s->pc += 2;
+    ext = read_im16(s);
     if (IS_USER(s) || (ext & SR_S) == 0) {
         gen_exception(s, addr, EXCP_PRIVILEGE);
         return;
@@ -3084,8 +3074,7 @@ DISAS_INSN(stop)
         return;
     }
 
-    ext = lduw_code(s->pc);
-    s->pc += 2;
+    ext = read_im16(s);
 
     gen_set_sr_im(s, ext, 0);
     tcg_gen_movi_i32(QREG_HALTED, 1);
@@ -3111,8 +3100,7 @@ DISAS_INSN(movec)
         return;
     }
 
-    ext = lduw_code(s->pc);
-    s->pc += 2;
+    ext = read_im16(s);
 
     if (ext & 0x8000) {
         reg = AREG(ext, 12);
@@ -3545,8 +3533,7 @@ DISAS_INSN(fscc_mem)
     TCGv addr;
     uint16_t ext;
 
-    ext = lduw_code(s->pc);
-    s->pc += 2;
+    ext = read_im16(s);
 
     taddr = gen_lea(s, insn, OS_BYTE);
     if (IS_NULL_QREG(taddr)) {
@@ -3572,8 +3559,7 @@ DISAS_INSN(fscc_reg)
     TCGv reg;
     uint16_t ext;
 
-    ext = lduw_code(s->pc);
-    s->pc += 2;
+    ext = read_im16(s);
 
     reg = DREG(insn, 0);
 
@@ -3641,8 +3627,7 @@ DISAS_INSN(mac)
         s->done_mac = 1;
     }
 
-    ext = lduw_code(s->pc);
-    s->pc += 2;
+    ext = read_im16(s);
 
     acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
     dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
@@ -4190,8 +4175,7 @@ static void disas_m68k_insn(CPUState * env, DisasContext *s)
     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
         tcg_gen_debug_insn_start(s->pc);
 
-    insn = lduw_code(s->pc);
-    s->pc += 2;
+    insn = read_im16(s);
 
     opcode_table[insn](s, insn);
 }
-- 
1.7.2.3

  parent reply	other threads:[~2011-08-17 20:49 UTC|newest]

Thread overview: 125+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-08-17 20:46 [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 001/111] linux-user: Signals processing is not thread-safe Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 002/111] linux-user: add qemu-wrapper Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 003/111] linux-user: define default cpu model in configure instead of linux-user/main.c Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 004/111] linux-user: specify the cpu model during configure Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 005/111] linux-user,m68k: display default cpu Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 006/111] linux-user: define new environment variables Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 007/111] linux-user: define a script to set binfmt using debian flavored tools Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 008/111] linux-user: define default cpu model in configure instead of linux-user/main.c Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 009/111] m68k: add tcg_gen_debug_insn_start() Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 010/111] m68k: define m680x0 CPUs and features Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 011/111] m68k: add missing accessing modes for some instructions Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 012/111] m68k: add Motorola 680x0 family common instructions Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 013/111] m68k: add Scc instruction with memory operand Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 014/111] m68k: add DBcc instruction Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 015/111] m68k: modify movem instruction to manage word Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 016/111] m68k: add 64bit divide Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 017/111] m68k: add 32bit and 64bit multiply Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 018/111] m68k: add word data size for suba/adda Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 019/111] m68k: add fpu Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 020/111] m68k: add "byte", "word" and memory shift Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 021/111] m68k: add "byte", "word" and memory rotate Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 022/111] m68k: add bitfield_mem, bitfield_reg Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 023/111] m68k: add variable offset/width to bitfield_reg/bitfield_mem Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 024/111] m68k: add cas Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 025/111] " Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 026/111] m68k: define fcntl constants Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 027/111] m68k: add DBcc instruction Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 028/111] m68k: allow fpu to manage double data type Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 029/111] m68k: allow fpu to manage double data type with fmove to <ea> Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 030/111] m68k: add FScc instruction Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 031/111] m68k: add single data type to gen_ea Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 032/111] m68k: add linkl instruction Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 033/111] m68k: Add fmovecr Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 034/111] m68k: correct typo on f64_to_i32() return type Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 035/111] m68k: improve CC_OP_LOGIC Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 036/111] m68k: correct neg condition code flags computation Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 037/111] Correct invalid use of "const void *" with "const uint8_t *" Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 038/111] m68k: add EA support for negx Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 039/111] m68k: add abcd instruction Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 040/111] m68k: add sbcd instruction Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 041/111] mm68k: add nbcd instruction Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 042/111] m68k: set X flag according size of operand Set X flag correctly for addsub, arith_im, addsubq Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 043/111] m68k: on 0 bit shift, don't update X flag Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 044/111] m68k: improve addx instructions Add (byte, word) opsize Add memory access Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 045/111] m68k: improve subx, negx instructions Add (byte, word) opsize Add memory access (subx) Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 046/111] m68k: improve asl/asr evaluate correclty the missing V flag Bryce Lanham
2011-08-17 20:46 ` Bryce Lanham [this message]
2011-08-17 20:46 ` [Qemu-devel] [PATCH 048/111] m68k: correct shift side effect for roxrl and roxll Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 049/111] m68k: asl/asr, clear C flag if shift count is 0 Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 050/111] m68k: lsl/lsr, " Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 051/111] m68k: correct divs.w and divu.w Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 052/111] m68k: correct flags with negl Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 053/111] m68k: for bitfield opcodes, correct operands corruption Bryce Lanham
2011-08-17 20:46 ` [Qemu-devel] [PATCH 054/111] m68k: Added ULL to 64 bit integer in helper.c Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 055/111] m68k: Correct bfclr in register case Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 056/111] m68k-linux-user: add '--enable-emulop' Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 057/111] m68k: correctly compute divsl Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 058/111] m68k: correctly compute divul Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 059/111] m68k: add m68030 definition Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 060/111] m68k: remove dead code Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 061/111] m68k: remove useless file m68k-qreg.h Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 062/111] m68k: FPU rework (draft) Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 063/111] m68k: some FPU debugging macros Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 064/111] m68k: more tests Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 065/111] m68k: correct compute gen_bitfield_cc() Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 066/111] m68k: add fgetexp Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 067/111] m68k: add fscale Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 068/111] m68k: correct addsubq Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 069/111] m68k: add fetox and flogn Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 070/111] m68k: initialize FRegs, define pickNaN() Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 071/111] m68k: correct cmpa comparison datatype Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 072/111] m68k: add flog10 Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 073/111] m68k: add cmpm instruction Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 074/111] m68k: add ftwotox instruction Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 075/111] m68k: better fpu traces Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 076/111] m68k: register source operand is always in extended size Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 077/111] m68k: add facos instruction Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 078/111] m68k: add ftan instruction Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 079/111] m68k: add fsin instruction Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 080/111] m68k: add fcos instruction Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 081/111] m68k: correct fpcr update Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 082/111] m68k: add fmod instruction Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 083/111] m68k: flush flags before negx instruction Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 084/111] m68k: correct fmovemx FP registers order Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 085/111] m68k: add fatan instruction Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 086/111] m68k: correct bfins instruction Bryce Lanham
2011-08-17 20:47 ` [Qemu-devel] [PATCH 087/111] m68k: fcmp correctly compares infinity Bryce Lanham
2011-08-17 22:35 ` [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions Anthony Liguori
2011-08-17 23:30   ` Bryce Lanham
2011-08-17 23:36     ` Peter Maydell
2011-08-18 16:05     ` Michael Roth
2011-08-18  7:02   ` Laurent Vivier
2011-08-18 11:12     ` François Revol
2011-08-18 14:02       ` Laurent Vivier
2011-08-18 19:42         ` Natalia Portillo
2011-08-18 19:57           ` Laurent Vivier
2011-08-18 20:13             ` Natalia Portillo
2011-08-18 20:51               ` Laurent Vivier
2011-08-19  2:14                 ` Natalia Portillo
2011-08-19  8:55                   ` François Revol
2011-08-19 15:52                     ` Natalia Portillo
2011-08-19 16:07                       ` Laurent Vivier
2011-08-19 20:08                         ` Anthony Liguori
2011-08-20 22:12                           ` Rob Landley
2011-08-20 22:12                     ` Rob Landley
2011-08-20 22:16                 ` Rob Landley
2011-08-20 21:06           ` Rob Landley
2011-08-20 20:57       ` Rob Landley
2011-08-20 21:16         ` Laurent Vivier
2011-08-20 22:28           ` Rob Landley
2011-08-20 22:39           ` Rob Landley
2011-08-20 23:24           ` Rob Landley
2011-08-20 20:55 ` Rob Landley
2011-08-20 23:17   ` Natalia Portillo
2011-08-20 23:42     ` Rob Landley
2011-08-21  0:23       ` Natalia Portillo
2011-08-21  0:50         ` Rob Landley
2011-08-21  2:02           ` Natalia Portillo
2011-08-21 22:14             ` Rob Landley
2011-08-22  2:15               ` Natalia Portillo
2011-08-23 12:30                 ` Rob Landley
2011-08-21 10:04       ` Laurent Vivier
2011-08-21 13:11         ` Natalia Portillo
2011-08-21 22:23         ` Rob Landley

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1313614076-28878-48-git-send-email-blanham@gmail.com \
    --to=blanham@gmail.com \
    --cc=laurent@vivier.eu \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).