From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:47430) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn3q-0000Bx-Dw for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:50:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qtn3b-0006sO-Ox for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:49:55 -0400 Received: from mail-gx0-f173.google.com ([209.85.161.173]:54221) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn3b-0006aR-MO for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:49:47 -0400 Received: by mail-gx0-f173.google.com with SMTP id 26so1230323gxk.4 for ; Wed, 17 Aug 2011 13:49:47 -0700 (PDT) From: Bryce Lanham Date: Wed, 17 Aug 2011 15:47:00 -0500 Message-Id: <1313614076-28878-56-git-send-email-blanham@gmail.com> In-Reply-To: <1313614076-28878-1-git-send-email-blanham@gmail.com> References: <1313614076-28878-1-git-send-email-blanham@gmail.com> Subject: [Qemu-devel] [PATCH 055/111] m68k: Correct bfclr in register case. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Laurent Vivier From: Laurent Vivier Apply a "not" on the mask to really clear bits with the "and"... (as it is done for bfclr in the memory case) Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index e0c6fa3..f93ad02 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -2769,6 +2769,7 @@ DISAS_INSN(bitfield_reg) tcg_gen_sar_i32(reg2, reg2, width); break; case 4: /* bfclr */ + tcg_gen_not_i32(mask, mask); tcg_gen_and_i32(reg, reg, mask); break; case 5: /* bfffo */ -- 1.7.2.3