From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:47940) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn4H-0000Np-S8 for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:50:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qtn4G-00076k-UE for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:50:29 -0400 Received: from mail-yx0-f173.google.com ([209.85.213.173]:36963) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn4G-0006fW-RW for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:50:28 -0400 Received: by mail-yx0-f173.google.com with SMTP id 3so1226800yxt.4 for ; Wed, 17 Aug 2011 13:50:28 -0700 (PDT) From: Bryce Lanham Date: Wed, 17 Aug 2011 15:47:29 -0500 Message-Id: <1313614076-28878-85-git-send-email-blanham@gmail.com> In-Reply-To: <1313614076-28878-1-git-send-email-blanham@gmail.com> References: <1313614076-28878-1-git-send-email-blanham@gmail.com> Subject: [Qemu-devel] [PATCH 084/111] m68k: correct fmovemx FP registers order. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Laurent Vivier From: Laurent Vivier seen with gcc testsuite, gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/930622-2.c allow to run gtk-demo, gimp ... Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index e9b6abc..14ce1f9 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3536,18 +3536,18 @@ static void gen_op_fmovem(DisasContext *s, uint32_t insn, uint32_t ext) mask = ext & 0x00FF; if (!is_load && (mode & 2) == 0) { - for (i = 7; i >= 0; i--, mask >>= 1) { - if (mask & 1) { + for (i = 7; i >= 0; i--, mask <<= 1) { + if (mask & 0x80) { gen_op_load_fpr_FP0(i); gen_store_FP0(s, opsize, addr); - if (mask != 1) + if ((mask & 0xff) != 0x80) tcg_gen_subi_i32(addr, addr, incr); } } tcg_gen_mov_i32(AREG(insn, 0), addr); } else{ - for (i = 0; i < 8; i++, mask >>=1) { - if (mask & 1) { + for (i = 0; i < 8; i++, mask <<=1) { + if (mask & 0x80) { if (is_load) { gen_load_FP0(s, opsize, addr); gen_op_store_fpr_FP0(i); @@ -3555,7 +3555,7 @@ static void gen_op_fmovem(DisasContext *s, uint32_t insn, uint32_t ext) gen_op_load_fpr_FP0(i); gen_store_FP0(s, opsize, addr); } - if (mask != 1 || (insn & 070) == 030) + if ((mask & 0xff) != 0x80 || (insn & 070) == 030) tcg_gen_addi_i32(addr, addr, incr); } } -- 1.7.2.3