From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:47970) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn4M-0000Ny-AT for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:50:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qtn4J-00077I-Ou for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:50:34 -0400 Received: from mail-yx0-f173.google.com ([209.85.213.173]:36963) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn4J-0006fW-Gp for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:50:31 -0400 Received: by mail-yx0-f173.google.com with SMTP id 3so1226800yxt.4 for ; Wed, 17 Aug 2011 13:50:31 -0700 (PDT) From: Bryce Lanham Date: Wed, 17 Aug 2011 15:47:31 -0500 Message-Id: <1313614076-28878-87-git-send-email-blanham@gmail.com> In-Reply-To: <1313614076-28878-1-git-send-email-blanham@gmail.com> References: <1313614076-28878-1-git-send-email-blanham@gmail.com> Subject: [Qemu-devel] [PATCH 086/111] m68k: correct bfins instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Laurent Vivier From: Laurent Vivier correctly update generated condition code. seen with gcc testsuite, gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/960301-1.c Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 34 +++++++++++++++++++++++++++++----- tests/m68k/Makefile | 3 ++- tests/m68k/bfins.S | 23 +++++++++++++++++++++++ 3 files changed, 54 insertions(+), 6 deletions(-) create mode 100644 tests/m68k/bfins.S diff --git a/target-m68k/translate.c b/target-m68k/translate.c index d4445fe..96ea93f 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3091,9 +3091,22 @@ DISAS_INSN(bitfield_reg) tmp1 = tcg_temp_new_i32(); gen_helper_rol32(tmp1, tmp, offset); - gen_logic_cc(s, tmp1, OS_LONG); reg2 = DREG(ext, 12); + if (op == 7) { + TCGv tmp2; + + tmp2 = tcg_temp_new_i32(); + tcg_gen_sub_i32(tmp2, tcg_const_i32(32), width); + tcg_gen_shl_i32(tmp2, reg2, tmp2); + tcg_gen_and_i32(tmp2, tmp2, mask); + gen_logic_cc(s, tmp2, OS_LONG); + + tcg_temp_free_i32(tmp1); + } else { + gen_logic_cc(s, tmp1, OS_LONG); + } + switch (op) { case 0: /* bftst */ break; @@ -3157,11 +3170,7 @@ static TCGv gen_bitfield_cc(DisasContext *s, tcg_gen_shri_i64(tmp64, tmp64, 32ULL); dest = tcg_temp_new_i32(); tcg_gen_trunc_i64_i32(dest, tmp64); - - /* compute cc */ - tcg_gen_and_i32(dest, dest, mask_cc); - gen_logic_cc(s, dest, OS_LONG); return dest; } @@ -3283,6 +3292,21 @@ DISAS_INSN(bitfield_mem) /* execute operation */ reg = DREG(ext, 12); + + if (op == 7) { + TCGv tmp1; + + tmp1 = tcg_temp_new_i32(); + tcg_gen_sub_i32(tmp1, tcg_const_i32(32), width); + tcg_gen_shl_i32(tmp1, reg, tmp1); + tcg_gen_and_i32(tmp1, tmp1, mask_cc); + gen_logic_cc(s, tmp1, OS_LONG); + + tcg_temp_free_i32(tmp1); + } else { + gen_logic_cc(s, val, OS_LONG); + } + switch (op) { case 0: /* bftst */ break; diff --git a/tests/m68k/Makefile b/tests/m68k/Makefile index 8e90986..d043aeb 100644 --- a/tests/m68k/Makefile +++ b/tests/m68k/Makefile @@ -1,4 +1,5 @@ -TESTS=fmovecr fmove fmovem fsub fdiv fmul fabs fgetexp fscale flogn fetox +TESTS=fmovecr fmove fmovem fsub fdiv fmul fabs fgetexp fscale flogn fetox \ + bfins all: $(TESTS) diff --git a/tests/m68k/bfins.S b/tests/m68k/bfins.S new file mode 100644 index 0000000..a0b27f9 --- /dev/null +++ b/tests/m68k/bfins.S @@ -0,0 +1,23 @@ + .include "trap.i" + + .data +.A: .long 0 + .text + .globl _start +_start: + move.l #0,%d1 + move.l #1,%d0 + bfins %d0,%d1,4,4 + move.l #3,%d0 + bfins %d0,%d1,8,2 + move.l #0,%d0 + bfins %d0,%d1,8,16 + + move.l #1,%d0 + lea .A,%a0 + bfins %d0,(%a0),4,4 + move.l #3,%d0 + bfins %d0,(%a0),8,2 + move.l #0,%d0 + bfins %d0,(%a0),8,16 + exit 0 -- 1.7.2.3