From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:51071) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn6Y-0001HM-1s for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:52:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qtn6X-0007ci-5Y for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:52:49 -0400 Received: from mail-yx0-f173.google.com ([209.85.213.173]:48683) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn6W-0007cd-Sg for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:52:49 -0400 Received: by yxt3 with SMTP id 3so1229870yxt.4 for ; Wed, 17 Aug 2011 13:52:48 -0700 (PDT) From: Bryce Lanham Date: Wed, 17 Aug 2011 15:52:38 -0500 Message-Id: <1313614358-29289-1-git-send-email-blanham@gmail.com> Subject: [Qemu-devel] [PATCH 088/111] m68k: allows bfins to manage correctly width = 32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Laurent Vivier From: Laurent Vivier tcg_gen_shl_i32() doesn't manage a shift of 32. As 32 >= width >= 1, we use two tcg_gen_shl_i32(): tcg_gen_shl_i32(1) and tcg_gen_shl_i32(width - 1) seen with gcc testsuite, gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/991118-1.c Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 96ea93f..52df274 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3215,7 +3215,11 @@ static void gen_bitfield_ins(TCGv offset, TCGv width, TCGv src, /* tmp = (1u << width) - 1; */ - tcg_gen_shl_i32(tmp, tcg_const_i32(1), width); + /* width is between 1 and 32 + * tcg_gen_shl_i32() cannot manage value 32 + */ + tcg_gen_subi_i32(tmp, width, 1); + tcg_gen_shl_i32(tmp, tcg_const_i32(2), tmp); tcg_gen_subi_i32(tmp, tmp, 1); /* tmp = tmp & src; */ -- 1.7.2.3