From: Bryce Lanham <blanham@gmail.com>
To: qemu-devel@nongnu.org
Cc: Laurent Vivier <laurent@vivier.eu>
Subject: [Qemu-devel] [PATCH 093/111] m68k: add exg instruction
Date: Wed, 17 Aug 2011 15:53:24 -0500 [thread overview]
Message-ID: <1313614410-29359-4-git-send-email-blanham@gmail.com> (raw)
In-Reply-To: <1313614410-29359-1-git-send-email-blanham@gmail.com>
From: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
target-m68k/translate.c | 33 ++++++++++++++++++++++++++++++++-
1 files changed, 32 insertions(+), 1 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index b749a76..8cb2728 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2538,10 +2538,41 @@ DISAS_INSN(and)
TCGv dest;
TCGv addr;
int opsize;
+ int exg_mode;
+ dest = tcg_temp_new();
+
+ /* exg */
+
+ exg_mode = insn & 0x1f8;
+ if (exg_mode == 0x140) {
+ /* exchange Dx and Dy */
+ src = DREG(insn, 9);
+ reg = DREG(insn, 0);
+ tcg_gen_mov_i32(dest, src);
+ tcg_gen_mov_i32(src, reg);
+ tcg_gen_mov_i32(reg, dest);
+ return;
+ } else if (exg_mode == 0x148) {
+ /* exchange Ax and Ay */
+ src = AREG(insn, 9);
+ reg = AREG(insn, 0);
+ tcg_gen_mov_i32(dest, src);
+ tcg_gen_mov_i32(src, reg);
+ tcg_gen_mov_i32(reg, dest);
+ return;
+ } else if (exg_mode == 0x188) {
+ /* exchange Dx and Ay */
+ src = DREG(insn, 9);
+ reg = AREG(insn, 0);
+ tcg_gen_mov_i32(dest, src);
+ tcg_gen_mov_i32(src, reg);
+ tcg_gen_mov_i32(reg, dest);
+ return;
+ }
+ /* and */
opsize = insn_opsize(insn, 6);
reg = DREG(insn, 9);
- dest = tcg_temp_new();
if (insn & 0x100) {
SRC_EA(src, opsize, -1, &addr);
tcg_gen_and_i32(dest, src, reg);
--
1.7.2.3
next prev parent reply other threads:[~2011-08-17 20:53 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-08-17 20:53 [Qemu-devel] [PATCH 090/111] m68k: correctly define and manage NaN Bryce Lanham
2011-08-17 20:53 ` [Qemu-devel] [PATCH 091/111] m68k: don't call gdb_register_coprocessor() twice Bryce Lanham
2011-08-17 20:53 ` [Qemu-devel] [PATCH 092/111] m68k: gdb FP registers are 96 bits Bryce Lanham
2011-08-17 20:53 ` Bryce Lanham [this message]
2011-08-17 20:53 ` [Qemu-devel] [PATCH 094/111] m68k: define floatx80_default_inf_high and floatx80_default_inf_low Bryce Lanham
2011-08-17 20:53 ` [Qemu-devel] [PATCH 095/111] m68k: add bkpt instruction Bryce Lanham
2011-08-17 20:53 ` [Qemu-devel] [PATCH 096/111] m68k: correctly convert floatx80<->long double Bryce Lanham
2011-08-17 20:53 ` [Qemu-devel] [PATCH 097/111] m68k: use expl() to compute exp_FP0() Bryce Lanham
2011-08-17 20:53 ` [Qemu-devel] [PATCH 098/111] m68k: use exp2l() to compute exp2_FP0() Bryce Lanham
2011-08-17 20:53 ` [Qemu-devel] [PATCH 099/111] m68k: use logl() to compute ln_FP0() Bryce Lanham
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