[Qemu-devel] [PATCH 100/111] m68k: use log10l() to compute log10_FP0()

[Qemu-devel] [PATCH 100/111] m68k: use log10l() to compute log10_FP0()

[Bryce Lanham]

From: Laurent Vivier <laurent@vivier.eu>

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/helper.c |   22 +++++++---------------
 1 files changed, 7 insertions(+), 15 deletions(-)

diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index f67a2d8..0c60093 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -1368,23 +1368,15 @@ void HELPER(ln_FP0)(CPUState *env)
 
 void HELPER(log10_FP0)(CPUState *env)
 {
-    float64 f, log2, log210;
-    floatx80 res;
-
-    /* log10(x) = log2(x) / log2(10) */
-
-    DBG_FPUH("log10_FP0 %Lg", floatx80_to_ldouble(FP0_to_floatx80(env)));
-    f = floatx80_to_float64(FP0_to_floatx80(env), &env->fp_status);
+    floatx80 val;
+    long double res;
 
-    log2 = float64_log2(f, &env->fp_status);
-    log210 = float64_log2(floatx80_to_float64(floatx80_10, &env->fp_status),
-                          &env->fp_status);
-    res = floatx80_div(float64_to_floatx80(log2, &env->fp_status),
-                       float64_to_floatx80(log210, &env->fp_status),
-                       &env->fp_status);
-    DBG_FPU(" = %Lg\n", floatx80_to_ldouble(res));
+    val = FP0_to_floatx80(env);
+    DBG_FPUH("log10_FP0 %Lg", floatx80_to_ldouble(val));
+    res = log10l(floatx80_to_ldouble(val));
+    DBG_FPU(" = %Lg\n", res);
 
-    floatx80_to_FP0(env, res);
+    floatx80_to_FP0(env, ldouble_to_floatx80(res));
 }
 
 void HELPER(atan_FP0)(CPUState *env)
-- 
1.7.2.3

[Qemu-devel] [PATCH 101/111] m68k: correctly load signed word into floating point register

[Bryce Lanham]

From: Laurent Vivier <laurent@vivier.eu>

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/translate.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 0a14597..987bd84 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -839,7 +839,7 @@ static inline void gen_load_FP0(DisasContext * s, int opsize, TCGv addr)
         gen_helper_exts32_FP0(cpu_env);
         break;
     case OS_WORD:
-        tcg_gen_qemu_ld16u(QREG_FP0H, addr, index);
+        tcg_gen_qemu_ld16s(QREG_FP0H, addr, index);
         gen_helper_exts32_FP0(cpu_env);
         break;
     case OS_LONG:
-- 
1.7.2.3

[Qemu-devel] [PATCH 102/111] m68k: add fcosh instruction

[Bryce Lanham]

From: Laurent Vivier <laurent@vivier.eu>

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/helper.c    |   15 +++++++++++++++
 target-m68k/helpers.h   |    1 +
 target-m68k/translate.c |    3 +++
 3 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 0c60093..c24eb85 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -1481,6 +1481,21 @@ void HELPER(abs_FP0)(CPUState *env)
     floatx80_to_FP0(env, res);
 }
 
+void HELPER(cosh_FP0)(CPUState *env)
+{
+    floatx80 res;
+    long double val;
+
+    res = FP0_to_floatx80(env);
+    val = floatx80_to_ldouble(res);
+
+    DBG_FPUH("cosh_FP0 %Lg", val);
+    val = coshl(val);
+    DBG_FPU(" = %Lg", val);
+    res = ldouble_to_floatx80(val);
+    floatx80_to_FP0(env, res);
+}
+
 void HELPER(chs_FP0)(CPUState *env)
 {
     floatx80 res;
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index 88a047b..31eb6ad 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -74,6 +74,7 @@ DEF_HELPER_1(exp10_FP0, void, env)
 DEF_HELPER_1(ln_FP0, void, env)
 DEF_HELPER_1(log10_FP0, void, env)
 DEF_HELPER_1(abs_FP0, void, env)
+DEF_HELPER_1(cosh_FP0, void, env)
 DEF_HELPER_1(chs_FP0, void, env)
 DEF_HELPER_1(acos_FP0, void, env)
 DEF_HELPER_1(cos_FP0, void, env)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 987bd84..987139b 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3751,6 +3751,9 @@ DISAS_INSN(fpu)
     case 0x18: case 0x58: case 0x5c: /* fabs */
         gen_helper_abs_FP0(cpu_env);
         break;
+    case 0x19:
+        gen_helper_cosh_FP0(cpu_env);
+        break;
     case 0x1a: case 0x5a: case 0x5e: /* fneg */
         gen_helper_chs_FP0(cpu_env);
         break;
-- 
1.7.2.3

[Qemu-devel] [PATCH 103/111] m68k: add fasin instruction

[Bryce Lanham]

From: Laurent Vivier <laurent@vivier.eu>

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/helper.c    |   15 +++++++++++++++
 target-m68k/helpers.h   |    1 +
 target-m68k/translate.c |    3 +++
 3 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index c24eb85..37d6774 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -1394,6 +1394,21 @@ void HELPER(atan_FP0)(CPUState *env)
     floatx80_to_FP0(env, res);
 }
 
+void HELPER(asin_FP0)(CPUState *env)
+{
+    floatx80 res;
+    long double val;
+
+    res = FP0_to_floatx80(env);
+    val = floatx80_to_ldouble(res);
+
+    DBG_FPUH("asin_FP0 %Lg", val);
+    val = asinl(val);
+    DBG_FPU(" = %Lg", val);
+    res = ldouble_to_floatx80(val);
+    floatx80_to_FP0(env, res);
+}
+
 void HELPER(sin_FP0)(CPUState *env)
 {
     floatx80 res;
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index 31eb6ad..229ca8f 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -66,6 +66,7 @@ DEF_HELPER_1(iround_FP0, void, env)
 DEF_HELPER_1(itrunc_FP0, void, env)
 DEF_HELPER_1(sqrt_FP0, void, env)
 DEF_HELPER_1(atan_FP0, void, env)
+DEF_HELPER_1(asin_FP0, void, env)
 DEF_HELPER_1(sin_FP0, void, env)
 DEF_HELPER_1(tan_FP0, void, env)
 DEF_HELPER_1(exp_FP0, void, env)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 987139b..fa9659d 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3727,6 +3727,9 @@ DISAS_INSN(fpu)
     case 0x0a:                       /* fatan */
         gen_helper_atan_FP0(cpu_env);
         break;
+    case 0x0c:
+        gen_helper_asin_FP0(cpu_env);
+        break;
     case 0x0e:                       /* fsin */
         gen_helper_sin_FP0(cpu_env);
         break;
-- 
1.7.2.3

[Qemu-devel] [PATCH 104/111] m68k: add fsincos instruction

[Bryce Lanham]

From: Laurent Vivier <laurent@vivier.eu>

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/helper.c    |   23 +++++++++++++++++++++++
 target-m68k/helpers.h   |    1 +
 target-m68k/translate.c |   17 +++++++++++++++++
 3 files changed, 41 insertions(+), 0 deletions(-)

diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 37d6774..5d34901 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -1086,6 +1086,12 @@ static inline void floatx80_to_FP0(CPUState *env, floatx80 res)
     env->fp0l = res.low;
 }
 
+static inline void floatx80_to_FP1(CPUState *env, floatx80 res)
+{
+    env->fp1h = res.high;
+    env->fp1l = res.low;
+}
+
 static inline int32_t FP0_to_int32(CPUState *env)
 {
     return env->fp0h;
@@ -1656,6 +1662,23 @@ void HELPER(mod_FP0_FP1)(CPUState *env)
     floatx80_to_FP0(env, res);
 }
 
+void HELPER(sincos_FP0_FP1)(CPUState *env)
+{
+    floatx80 res;
+    long double val, valsin, valcos;
+
+    res = FP0_to_floatx80(env);
+    val = floatx80_to_ldouble(res);
+
+    DBG_FPUH("sincos_FP0 %Lg", val);
+    sincosl(val, &valsin, &valcos);
+    DBG_FPU(" = %Lg, %Lg", valsin, valcos);
+    res = ldouble_to_floatx80(valsin);
+    floatx80_to_FP0(env, res);
+    res = ldouble_to_floatx80(valcos);
+    floatx80_to_FP1(env, res);
+}
+
 void HELPER(fcmp_FP0_FP1)(CPUState *env)
 {
     /* ??? This may incorrectly raise exceptions.  */
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index 229ca8f..154c183 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -86,6 +86,7 @@ DEF_HELPER_1(sub_FP0_FP1, void, env)
 DEF_HELPER_1(mul_FP0_FP1, void, env)
 DEF_HELPER_1(div_FP0_FP1, void, env)
 DEF_HELPER_1(mod_FP0_FP1, void, env)
+DEF_HELPER_1(sincos_FP0_FP1, void, env)
 DEF_HELPER_1(fcmp_FP0_FP1, void, env)
 DEF_HELPER_1(compare_FP0, i32, env)
 
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index fa9659d..e714eb4 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -220,6 +220,16 @@ static void gen_op_store_fpr_FP0(int freg)
                    offsetof(FPReg, d.low));
 }
 
+static void gen_op_store_fpr_FP1(int freg)
+{
+    tcg_gen_st16_i32(QREG_FP1H, cpu_env,
+                     offsetof(CPUM68KState, fregs[freg]) +
+                     offsetof(FPReg, d.high));
+    tcg_gen_st_i64(QREG_FP1L, cpu_env,
+                   offsetof(CPUM68KState, fregs[freg]) +
+                   offsetof(FPReg, d.low));
+}
+
 static void gen_op_load_fpr_FP1(int freg)
 {
     tcg_gen_ld16u_i32(QREG_FP1H, cpu_env,
@@ -3801,6 +3811,13 @@ DISAS_INSN(fpu)
         gen_op_load_fpr_FP1(REG(ext, 7));
         gen_helper_sub_FP0_FP1(cpu_env);
         break;
+    case 0x30: case 0x31: case 0x32:
+    case 0x33: case 0x34: case 0x35:
+    case 0x36: case 0x37:
+        gen_helper_sincos_FP0_FP1(cpu_env);
+        gen_op_store_fpr_FP0(REG(ext, 7));	/* sin */
+        gen_op_store_fpr_FP1(REG(ext, 0));	/* cos */
+        break;
     case 0x38: /* fcmp */
         gen_op_load_fpr_FP1(REG(ext, 7));
         gen_helper_fcmp_FP0_FP1(cpu_env);
-- 
1.7.2.3

[Qemu-devel] [PATCH 105/111] m68k: add fsinh instruction

[Bryce Lanham]

From: Laurent Vivier <laurent@vivier.eu>

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/helper.c    |   15 +++++++++++++++
 target-m68k/helpers.h   |    1 +
 target-m68k/translate.c |    3 +++
 3 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 5d34901..fc1b560 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -1331,6 +1331,21 @@ void HELPER(iround_FP0)(CPUState *env)
     floatx80_to_FP0(env, res);
 }
 
+void HELPER(sinh_FP0)(CPUState *env)
+{
+    floatx80 res;
+    long double val;
+
+    res = FP0_to_floatx80(env);
+    val = floatx80_to_ldouble(res);
+
+    DBG_FPUH("sinh_FP0 %Lg", val);
+    val = sinhl(val);
+    DBG_FPU(" = %Lg", val);
+    res = ldouble_to_floatx80(val);
+    floatx80_to_FP0(env, res);
+}
+
 void HELPER(itrunc_FP0)(CPUState *env)
 {
     floatx80 res;
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index 154c183..e77b9b7 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -63,6 +63,7 @@ DEF_HELPER_4(fmovem, void, env, i32, i32, i32)
 DEF_HELPER_2(set_fpcr, void, env, i32)
 DEF_HELPER_2(const_FP0, void, env, i32)
 DEF_HELPER_1(iround_FP0, void, env)
+DEF_HELPER_1(sinh_FP0, void, env)
 DEF_HELPER_1(itrunc_FP0, void, env)
 DEF_HELPER_1(sqrt_FP0, void, env)
 DEF_HELPER_1(atan_FP0, void, env)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index e714eb4..c43bfe8 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3727,6 +3727,9 @@ DISAS_INSN(fpu)
         gen_helper_iround_FP0(cpu_env);
         round = 0;
         break;
+    case 2: /* fsinh */
+        gen_helper_sinh_FP0(cpu_env);
+        break;
     case 3: /* fintrz */
         gen_helper_itrunc_FP0(cpu_env);
         round = 0;
-- 
1.7.2.3

[Qemu-devel] [PATCH 106/111] m68k: add ftanh instruction

[Bryce Lanham]

From: Laurent Vivier <laurent@vivier.eu>

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/helper.c    |   15 +++++++++++++++
 target-m68k/helpers.h   |    1 +
 target-m68k/translate.c |    3 +++
 3 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index fc1b560..9269b48 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -1445,6 +1445,21 @@ void HELPER(sin_FP0)(CPUState *env)
     floatx80_to_FP0(env, res);
 }
 
+void HELPER(tanh_FP0)(CPUState *env)
+{
+    floatx80 res;
+    long double val;
+
+    res = FP0_to_floatx80(env);
+    val = floatx80_to_ldouble(res);
+
+    DBG_FPUH("tanh_FP0 %Lg", val);
+    val = tanhl(val);
+    DBG_FPU(" = %Lg", val);
+    res = ldouble_to_floatx80(val);
+    floatx80_to_FP0(env, res);
+}
+
 void HELPER(tan_FP0)(CPUState *env)
 {
     floatx80 res;
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index e77b9b7..3c8fc60 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -69,6 +69,7 @@ DEF_HELPER_1(sqrt_FP0, void, env)
 DEF_HELPER_1(atan_FP0, void, env)
 DEF_HELPER_1(asin_FP0, void, env)
 DEF_HELPER_1(sin_FP0, void, env)
+DEF_HELPER_1(tanh_FP0, void, env)
 DEF_HELPER_1(tan_FP0, void, env)
 DEF_HELPER_1(exp_FP0, void, env)
 DEF_HELPER_1(exp2_FP0, void, env)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index c43bfe8..26ab027 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3737,6 +3737,9 @@ DISAS_INSN(fpu)
     case 4: case 0x41: case 0x45: /* fsqrt */
         gen_helper_sqrt_FP0(cpu_env);
         break;
+    case 0x09:                       /* ftanh */
+        gen_helper_tanh_FP0(cpu_env);
+        break;
     case 0x0a:                       /* fatan */
         gen_helper_atan_FP0(cpu_env);
         break;
-- 
1.7.2.3

[Qemu-devel] [PATCH 107/111] m68k: add flognp1 instruction

[Bryce Lanham]

From: Laurent Vivier <laurent@vivier.eu>

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/helper.c    |   13 +++++++++++++
 target-m68k/helpers.h   |    1 +
 target-m68k/translate.c |    3 +++
 3 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 9269b48..f9a35d5 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -1374,6 +1374,19 @@ void HELPER(sqrt_FP0)(CPUState *env)
     floatx80_to_FP0(env, res);
 }
 
+void HELPER(lognp1_FP0)(CPUState *env)
+{
+    floatx80 val;
+    long double res;
+
+    val = FP0_to_floatx80(env);
+    DBG_FPUH("lognp1_FP0 %Lg", floatx80_to_ldouble(val));
+    res = logl(floatx80_to_ldouble(val) + 1.0);
+    DBG_FPU(" = %Lg\n", res);
+
+    floatx80_to_FP0(env, ldouble_to_floatx80(res));
+}
+
 void HELPER(ln_FP0)(CPUState *env)
 {
     floatx80 val;
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index 3c8fc60..c043c54 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -66,6 +66,7 @@ DEF_HELPER_1(iround_FP0, void, env)
 DEF_HELPER_1(sinh_FP0, void, env)
 DEF_HELPER_1(itrunc_FP0, void, env)
 DEF_HELPER_1(sqrt_FP0, void, env)
+DEF_HELPER_1(lognp1_FP0, void, env)
 DEF_HELPER_1(atan_FP0, void, env)
 DEF_HELPER_1(asin_FP0, void, env)
 DEF_HELPER_1(sin_FP0, void, env)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 26ab027..f4f10f4 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3737,6 +3737,9 @@ DISAS_INSN(fpu)
     case 4: case 0x41: case 0x45: /* fsqrt */
         gen_helper_sqrt_FP0(cpu_env);
         break;
+    case 6:                          /* flognp1 */
+        gen_helper_lognp1_FP0(cpu_env);
+        break;
     case 0x09:                       /* ftanh */
         gen_helper_tanh_FP0(cpu_env);
         break;
-- 
1.7.2.3

[Qemu-devel] [PATCH 108/111] m68k: add fatanh instruction

[Bryce Lanham]

From: Laurent Vivier <laurent@vivier.eu>

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/helper.c    |   15 +++++++++++++++
 target-m68k/helpers.h   |    1 +
 target-m68k/translate.c |    5 ++++-
 3 files changed, 20 insertions(+), 1 deletions(-)

diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index f9a35d5..93a178a 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -1443,6 +1443,21 @@ void HELPER(asin_FP0)(CPUState *env)
     floatx80_to_FP0(env, res);
 }
 
+void HELPER(atanh_FP0)(CPUState *env)
+{
+    floatx80 res;
+    long double val;
+
+    res = FP0_to_floatx80(env);
+    val = floatx80_to_ldouble(res);
+
+    DBG_FPUH("atanh_FP0 %Lg", val);
+    val = atanhl(val);
+    DBG_FPU(" = %Lg", val);
+    res = ldouble_to_floatx80(val);
+    floatx80_to_FP0(env, res);
+}
+
 void HELPER(sin_FP0)(CPUState *env)
 {
     floatx80 res;
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index c043c54..373660e 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -69,6 +69,7 @@ DEF_HELPER_1(sqrt_FP0, void, env)
 DEF_HELPER_1(lognp1_FP0, void, env)
 DEF_HELPER_1(atan_FP0, void, env)
 DEF_HELPER_1(asin_FP0, void, env)
+DEF_HELPER_1(atanh_FP0, void, env)
 DEF_HELPER_1(sin_FP0, void, env)
 DEF_HELPER_1(tanh_FP0, void, env)
 DEF_HELPER_1(tan_FP0, void, env)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index f4f10f4..71cbffb 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3746,9 +3746,12 @@ DISAS_INSN(fpu)
     case 0x0a:                       /* fatan */
         gen_helper_atan_FP0(cpu_env);
         break;
-    case 0x0c:
+    case 0x0c:                       /* fasin */
         gen_helper_asin_FP0(cpu_env);
         break;
+    case 0x0d:                       /* fatanh */
+        gen_helper_atanh_FP0(cpu_env);
+        break;
     case 0x0e:                       /* fsin */
         gen_helper_sin_FP0(cpu_env);
         break;
-- 
1.7.2.3

[Qemu-devel] [PATCH 109/111] m68k: first draft of q800 emulation (not working)

[Bryce Lanham]

From: Laurent Vivier <laurent@vivier.eu>

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 Makefile.target      |    1 +
 hw/m68k_mac.c        |  176 ++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/mcf5208.c         |    2 +-
 target-m68k/helper.c |   27 +++++++-
 4 files changed, 201 insertions(+), 5 deletions(-)
 create mode 100644 hw/m68k_mac.c

diff --git a/Makefile.target b/Makefile.target
index a486aa9..1db4c39 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -374,6 +374,7 @@ obj-sh4-y += ide/mmio.o
 
 obj-m68k-y = an5206.o mcf5206.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
 obj-m68k-y += m68k-semi.o dummy_m68k.o
+obj-m68k-y += m68k_mac.o
 
 obj-s390x-y = s390-virtio-bus.o s390-virtio.o
 
diff --git a/hw/m68k_mac.c b/hw/m68k_mac.c
new file mode 100644
index 0000000..c1daff0
--- /dev/null
+++ b/hw/m68k_mac.c
@@ -0,0 +1,176 @@
+/*
+ * QEMU Motorla 680x0 Macintosh hardware System Emulator
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw.h"
+#include "boards.h"
+#include "elf.h"
+#include "loader.h"
+
+static void q800_init(ram_addr_t ram_size,
+                       const char *boot_device,
+                       const char *kernel_filename,
+                       const char *kernel_cmdline,
+                       const char *initrd_filename,
+                       const char *cpu_model)
+{
+    CPUState *env = NULL;
+    int linux_boot;
+    ram_addr_t ram_offset;
+    int32_t kernel_size;
+    uint64_t elf_entry;
+#if 0
+    char *filename;
+    qemu_irq *pic, **heathrow_irqs;
+    int i;
+    ram_addr_t bios_offset;
+    uint32_t kernel_base, initrd_base;
+    int32_t initrd_size;
+    PCIBus *pci_bus;
+    MacIONVRAMState *nvr;
+    int bios_size;
+    int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
+    int escc_mem_index, ide_mem_index[2];
+    uint16_t ppc_boot_device;
+    DriveInfo * hd[MAX_IDE_BUS * MAX_IDE_DEVS];
+    void *fw_cfg;
+    void *dbdma;
+#endif
+
+    linux_boot = (kernel_filename != NULL);
+
+    /* init CPUs */
+    if (cpu_model == NULL) {
+        cpu_model = "m68040";
+    }
+    env = cpu_init(cpu_model);
+    if (!env) {
+            hw_error("qemu: unable to find m68k CPU definition\n");
+            exit(1);
+    }
+    qemu_register_reset((QEMUResetHandler *)&cpu_reset, env);
+
+    ram_offset = qemu_ram_alloc(NULL, "m68k_mac.ram", ram_size);
+    cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
+
+#if 0
+    /* allocate and load BIOS */
+    bios_offset = qemu_ram_alloc(NULL, "ppc_heathrow.bios", BIOS_SIZE);
+    if (bios_name == NULL) {
+        bios_name = PROM_FILENAME;
+    }
+    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
+    cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE,
+                                 bios_offset | IO_MEM_ROM);
+
+    /* Load OpenBIOS (ELF) */
+    if (filename) {
+        bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL,
+                             1, ELF_MACHINE, 0);
+        qemu_free(filename);
+    } else {
+        bios_size = -1;
+    }
+    if (bios_size < 0 || bios_size > BIOS_SIZE) {
+        hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
+        exit(1);
+    }
+#endif
+
+    if (linux_boot) {
+
+        kernel_size = load_elf(kernel_filename, NULL, NULL,
+                               &elf_entry, NULL, NULL, 1,
+                               ELF_MACHINE, 0);
+        if (kernel_size < 0) {
+            hw_error("qemu: could not load kernel '%s'\n",
+                      kernel_filename);
+            exit(1);
+        }
+        env->pc = elf_entry;
+#if 0
+        /* load initrd */
+        if (initrd_filename) {
+            initrd_base = INITRD_LOAD_ADDR;
+            initrd_size = load_image_targphys(initrd_filename, initrd_base,
+                                              ram_size - initrd_base);
+            if (initrd_size < 0) {
+                hw_error("qemu: could not load initial ram disk '%s'\n",
+                         initrd_filename);
+                exit(1);
+            }
+        } else {
+            initrd_base = 0;
+            initrd_size = 0;
+        }
+#endif
+    }
+
+#if 0
+    /* XXX: we register only 1 output pin for heathrow PIC */
+    heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
+    heathrow_irqs[0] =
+        qemu_mallocz(smp_cpus * sizeof(qemu_irq)*1);
+    /* Connect the heathrow PIC outputs to the 6xx bus */
+    for (i = 0; i < smp_cpus; i++) {
+        switch (PPC_INPUT(env)) {
+        case PPC_FLAGS_INPUT_6xx:
+            heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
+            heathrow_irqs[i][0] =
+                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
+            break;
+        default:
+            hw_error("Bus model not supported on OldWorld Mac machine\n");
+        }
+    }
+
+    escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
+                               serial_hds[1], ESCC_CLOCK, 4);
+
+    /* cuda also initialize ADB */
+    cuda_init(&cuda_mem_index, pic[0x12]);
+
+    adb_kbd_init(&adb_bus);
+    adb_mouse_init(&adb_bus);
+
+    macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index,
+               dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index,
+               escc_mem_index);
+
+    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) {
+        graphic_depth = 15;
+    }
+#endif
+}
+
+static QEMUMachine q800_machine = {
+    .name = "q800",
+    .desc = "Macintosh Quadra 800",
+    .init = q800_init,
+    .max_cpus = 1,
+    .is_default = 1,
+};
+
+static void q800_machine_init(void)
+{
+    qemu_register_machine(&q800_machine);
+}
+
+machine_init(q800_machine_init);
diff --git a/hw/mcf5208.c b/hw/mcf5208.c
index 78fbc5f..8425bca 100644
--- a/hw/mcf5208.c
+++ b/hw/mcf5208.c
@@ -295,7 +295,7 @@ static QEMUMachine mcf5208evb_machine = {
     .name = "mcf5208evb",
     .desc = "MCF5206EVB",
     .init = mcf5208evb_init,
-    .is_default = 1,
+    .is_default = 0,
 };
 
 static void mcf5208evb_machine_init(void)
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 93a178a..71294c0 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -281,8 +281,11 @@ void cpu_reset(CPUM68KState *env)
         log_cpu_state(env, 0);
     }
 
+#if defined(CONFIG_USER_ONLY)
     memset(env, 0, offsetof(CPUM68KState, breakpoints));
-#if !defined (CONFIG_USER_ONLY)
+    /* TODO: We should set PC from the interrupt vector.  */
+    env->pc = 0;
+#else
     env->sr = 0x2700;
 #endif
     m68k_switch_sp(env);
@@ -296,8 +299,6 @@ void cpu_reset(CPUM68KState *env)
     env->fp1l = floatx80_default_nan.low;
 
     env->cc_op = CC_OP_FLAGS;
-    /* TODO: We should set PC from the interrupt vector.  */
-    env->pc = 0;
     tlb_flush(env, 1);
 }
 
@@ -472,7 +473,7 @@ set_x:
     env->cc_dest = flags;
 }
 
-void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val)
+void HELPER(movec_to)(CPUM68KState * env, uint32_t reg, uint32_t val)
 {
     switch (reg) {
     case 0x02: /* CACR */
@@ -492,6 +493,24 @@ void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val)
     }
 }
 
+uint32_t HELPER(movec_from)(CPUM68KState * env, uint32_t reg)
+{
+    switch (reg) {
+    case 0x02: /* CACR */
+        return env->cacr;
+    case 0x04: case 0x05: case 0x06: case 0x07: /* ACR[0-3] */
+        /* TODO: Implement Access Control Registers.  */
+        return 0;
+    case 0x801: /* VBR */
+        return env->vbr;
+        break;
+    /* TODO: Implement control registers.  */
+    default:
+        cpu_abort(env, "Unimplemented control register read 0x%x\n",
+                  reg);
+    }
+}
+
 void HELPER(set_macsr)(CPUM68KState *env, uint32_t val)
 {
     uint32_t acc;
-- 
1.7.2.3

[Qemu-devel] [PATCH 110/111] m68k: add movec instruction

[Bryce Lanham]

From: Laurent Vivier <laurent@vivier.eu>

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/helpers.h   |    3 ++-
 target-m68k/translate.c |   11 ++++++++---
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index 373660e..d321874 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -48,7 +48,8 @@ DEF_HELPER_2(xflag_lt_i8, i32, i32, i32)
 DEF_HELPER_2(xflag_lt_i16, i32, i32, i32)
 DEF_HELPER_2(xflag_lt_i32, i32, i32, i32)
 DEF_HELPER_2(set_sr, void, env, i32)
-DEF_HELPER_3(movec, void, env, i32, i32)
+DEF_HELPER_3(movec_to, void, env, i32, i32)
+DEF_HELPER_2(movec_from, i32, env, i32)
 
 DEF_HELPER_1(exts32_FP0, void, env)
 DEF_HELPER_1(extf32_FP0, void, env)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 71cbffb..b4b36f7 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3532,7 +3532,11 @@ DISAS_INSN(movec)
     } else {
         reg = DREG(ext, 12);
     }
-    gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg);
+    if (insn & 1) {
+        gen_helper_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
+    } else {
+        gen_helper_movec_from(reg, cpu_env, tcg_const_i32(ext & 0xfff));
+    }
     gen_lookup_tb(s);
 }
 
@@ -4435,7 +4439,7 @@ void register_m68k_insns (CPUM68KState *env)
     INSN(move_to_ccr, 44c0, ffc0, M68000);
     INSN(not,       4680, fff8, CF_ISA_A);
     INSN(not,       4600, ff00, M68000);
-    INSN(undef,     46c0, ffc0, M68000);
+    INSN(move_to_sr, 46c0, ffc0, M68000);
     INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
     INSN(nbcd,      4800, ffc0, M68000);
     INSN(linkl,     4808, fff8, M68000);
@@ -4481,7 +4485,8 @@ void register_m68k_insns (CPUM68KState *env)
     INSN(rte,       4e73, ffff, M68000);
     INSN(rts,       4e75, ffff, CF_ISA_A);
     INSN(rts,       4e75, ffff, M68000);
-    INSN(movec,     4e7b, ffff, CF_ISA_A);
+    INSN(movec,     4e7a, fffe, CF_ISA_A);
+    INSN(movec,     4e7a, fffe, M68000);
     INSN(jump,      4e80, ffc0, CF_ISA_A);
     INSN(jump,      4e80, ffc0, M68000);
     INSN(jump,      4ec0, ffc0, CF_ISA_A);
-- 
1.7.2.3

[Qemu-devel] [PATCH 111/111] m68k: move from sr can use effective addresse on m68k

[Bryce Lanham]

From: Laurent Vivier <laurent@vivier.eu>

---
 target-m68k/translate.c |    8 +++-----
 1 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index b4b36f7..0be011e 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3443,16 +3443,14 @@ DISAS_INSN(strldsr)
 
 DISAS_INSN(move_from_sr)
 {
-    TCGv reg;
     TCGv sr;
 
-    if (IS_USER(s)) {
+    if (IS_USER(s)) {    /* FIXME: not privileged on 68000 */
         gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
         return;
     }
     sr = gen_get_sr(s);
-    reg = DREG(insn, 0);
-    gen_partset_reg(OS_WORD, reg, sr);
+    DEST_EA(insn, OS_WORD, sr, NULL);
 }
 
 DISAS_INSN(move_to_sr)
@@ -4424,7 +4422,7 @@ void register_m68k_insns (CPUM68KState *env)
     INSN(negx,      4000, ff00, M68000);
     INSN(undef,     40c0, ffc0, M68000);
     INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
-    INSN(move_from_sr, 40c0, fff8, M68000);
+    INSN(move_from_sr, 40c0, ffc0, M68000);
     INSN(lea,       41c0, f1c0, CF_ISA_A);
     INSN(lea,       41c0, f1c0, M68000);
     INSN(clr,       4200, ff00, CF_ISA_A);
-- 
1.7.2.3