[Qemu-devel] [PATCH 104/111] m68k: add fsincos instruction

[Bryce Lanham <blanham@gmail.com>]

From: Laurent Vivier <laurent@vivier.eu>

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/helper.c    |   23 +++++++++++++++++++++++
 target-m68k/helpers.h   |    1 +
 target-m68k/translate.c |   17 +++++++++++++++++
 3 files changed, 41 insertions(+), 0 deletions(-)

diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 37d6774..5d34901 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -1086,6 +1086,12 @@ static inline void floatx80_to_FP0(CPUState *env, floatx80 res)
     env->fp0l = res.low;
 }
 
+static inline void floatx80_to_FP1(CPUState *env, floatx80 res)
+{
+    env->fp1h = res.high;
+    env->fp1l = res.low;
+}
+
 static inline int32_t FP0_to_int32(CPUState *env)
 {
     return env->fp0h;
@@ -1656,6 +1662,23 @@ void HELPER(mod_FP0_FP1)(CPUState *env)
     floatx80_to_FP0(env, res);
 }
 
+void HELPER(sincos_FP0_FP1)(CPUState *env)
+{
+    floatx80 res;
+    long double val, valsin, valcos;
+
+    res = FP0_to_floatx80(env);
+    val = floatx80_to_ldouble(res);
+
+    DBG_FPUH("sincos_FP0 %Lg", val);
+    sincosl(val, &valsin, &valcos);
+    DBG_FPU(" = %Lg, %Lg", valsin, valcos);
+    res = ldouble_to_floatx80(valsin);
+    floatx80_to_FP0(env, res);
+    res = ldouble_to_floatx80(valcos);
+    floatx80_to_FP1(env, res);
+}
+
 void HELPER(fcmp_FP0_FP1)(CPUState *env)
 {
     /* ??? This may incorrectly raise exceptions.  */
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index 229ca8f..154c183 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -86,6 +86,7 @@ DEF_HELPER_1(sub_FP0_FP1, void, env)
 DEF_HELPER_1(mul_FP0_FP1, void, env)
 DEF_HELPER_1(div_FP0_FP1, void, env)
 DEF_HELPER_1(mod_FP0_FP1, void, env)
+DEF_HELPER_1(sincos_FP0_FP1, void, env)
 DEF_HELPER_1(fcmp_FP0_FP1, void, env)
 DEF_HELPER_1(compare_FP0, i32, env)
 
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index fa9659d..e714eb4 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -220,6 +220,16 @@ static void gen_op_store_fpr_FP0(int freg)
                    offsetof(FPReg, d.low));
 }
 
+static void gen_op_store_fpr_FP1(int freg)
+{
+    tcg_gen_st16_i32(QREG_FP1H, cpu_env,
+                     offsetof(CPUM68KState, fregs[freg]) +
+                     offsetof(FPReg, d.high));
+    tcg_gen_st_i64(QREG_FP1L, cpu_env,
+                   offsetof(CPUM68KState, fregs[freg]) +
+                   offsetof(FPReg, d.low));
+}
+
 static void gen_op_load_fpr_FP1(int freg)
 {
     tcg_gen_ld16u_i32(QREG_FP1H, cpu_env,
@@ -3801,6 +3811,13 @@ DISAS_INSN(fpu)
         gen_op_load_fpr_FP1(REG(ext, 7));
         gen_helper_sub_FP0_FP1(cpu_env);
         break;
+    case 0x30: case 0x31: case 0x32:
+    case 0x33: case 0x34: case 0x35:
+    case 0x36: case 0x37:
+        gen_helper_sincos_FP0_FP1(cpu_env);
+        gen_op_store_fpr_FP0(REG(ext, 7));	/* sin */
+        gen_op_store_fpr_FP1(REG(ext, 0));	/* cos */
+        break;
     case 0x38: /* fcmp */
         gen_op_load_fpr_FP1(REG(ext, 7));
         gen_helper_fcmp_FP0_FP1(cpu_env);
-- 
1.7.2.3