From: Alexander Graf <agraf@suse.de>
To: qemu-devel@nongnu.org
Cc: scottwood@freescale.com
Subject: [Qemu-devel] [PATCH 2/3] PPC: E500: Inject SPE exception on invalid SPE access
Date: Tue, 23 Aug 2011 06:55:43 +0200 [thread overview]
Message-ID: <1314075344-20839-3-git-send-email-agraf@suse.de> (raw)
In-Reply-To: <1314075344-20839-2-git-send-email-agraf@suse.de>
When accessing an SPE instruction despite it being not available,
throw an SPE exception instead of an APU exception. That way the
guest knows what's going on and actually uses SPE.
Reported-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate.c | 78 ++++++++++++++++++++++++------------------------
1 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index fd7c208..f36363a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6622,7 +6622,7 @@ static inline void gen_evmra(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
@@ -6693,7 +6693,7 @@ static inline void gen_speundef(DisasContext *ctx)
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
@@ -6704,7 +6704,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
@@ -6729,7 +6729,7 @@ GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
TCGv_i32 t0 = tcg_temp_local_new_i32(); \
@@ -6750,7 +6750,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
@@ -6770,7 +6770,7 @@ GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
TCGv_i32 t0 = tcg_temp_local_new_i32(); \
@@ -6791,7 +6791,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
@@ -6829,7 +6829,7 @@ GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
TCGv_i32 t0 = tcg_temp_local_new_i32(); \
@@ -6855,7 +6855,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
@@ -6933,7 +6933,7 @@ GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
static inline void gen_evmergehi(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
@@ -6962,7 +6962,7 @@ GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
TCGv_i32 t0 = tcg_temp_local_new_i32(); \
@@ -6983,7 +6983,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
@@ -7001,7 +7001,7 @@ GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
int l1 = gen_new_label(); \
@@ -7041,7 +7041,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
int l1 = gen_new_label(); \
@@ -7084,7 +7084,7 @@ static inline void gen_brinc(DisasContext *ctx)
static inline void gen_evmergelo(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
@@ -7103,7 +7103,7 @@ static inline void gen_evmergelo(DisasContext *ctx)
static inline void gen_evmergehilo(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
@@ -7122,7 +7122,7 @@ static inline void gen_evmergehilo(DisasContext *ctx)
static inline void gen_evmergelohi(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
@@ -7245,7 +7245,7 @@ static inline void gen_evmwumi(DisasContext *ctx)
TCGv_i64 t0, t1;
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
@@ -7274,7 +7274,7 @@ static inline void gen_evmwumia(DisasContext *ctx)
TCGv_i64 tmp;
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
@@ -7294,7 +7294,7 @@ static inline void gen_evmwumiaa(DisasContext *ctx)
TCGv_i64 tmp;
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
@@ -7327,7 +7327,7 @@ static inline void gen_evmwsmi(DisasContext *ctx)
TCGv_i64 t0, t1;
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
@@ -7746,7 +7746,7 @@ static void glue(gen_, name)(DisasContext *ctx)
{ \
TCGv t0; \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
gen_set_access_type(ctx, ACCESS_INT); \
@@ -7904,7 +7904,7 @@ static inline void gen_##name(DisasContext *ctx) \
TCGv_i32 t0, t1; \
TCGv_i64 t2; \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
t0 = tcg_temp_new_i32(); \
@@ -7925,7 +7925,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
@@ -7936,7 +7936,7 @@ static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i32 t0, t1; \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
t0 = tcg_temp_new_i32(); \
@@ -7951,7 +7951,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
@@ -7992,7 +7992,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
@@ -8003,7 +8003,7 @@ static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i64 t0, t1; \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
t0 = tcg_temp_new_i64(); \
@@ -8019,7 +8019,7 @@ static inline void gen_##name(DisasContext *ctx) \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
@@ -8030,7 +8030,7 @@ static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i64 t0, t1; \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
t0 = tcg_temp_new_i64(); \
@@ -8052,7 +8052,7 @@ GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
static inline void gen_evfsabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
@@ -8065,7 +8065,7 @@ static inline void gen_evfsabs(DisasContext *ctx)
static inline void gen_evfsnabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
@@ -8078,7 +8078,7 @@ static inline void gen_evfsnabs(DisasContext *ctx)
static inline void gen_evfsneg(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
@@ -8134,7 +8134,7 @@ GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
static inline void gen_efsabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
@@ -8142,7 +8142,7 @@ static inline void gen_efsabs(DisasContext *ctx)
static inline void gen_efsnabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
@@ -8150,7 +8150,7 @@ static inline void gen_efsnabs(DisasContext *ctx)
static inline void gen_efsneg(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
@@ -8202,7 +8202,7 @@ GEN_SPEFPUOP_ARITH2_64_64(efddiv);
static inline void gen_efdabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
@@ -8215,7 +8215,7 @@ static inline void gen_efdabs(DisasContext *ctx)
static inline void gen_efdnabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
@@ -8228,7 +8228,7 @@ static inline void gen_efdnabs(DisasContext *ctx)
static inline void gen_efdneg(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
--
1.6.0.2
next prev parent reply other threads:[~2011-08-23 4:55 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-08-23 4:55 [Qemu-devel] [PATCH 0/3] PPC: E500: Support SPE guest Alexander Graf
2011-08-23 4:55 ` [Qemu-devel] [PATCH 1/3] PPC: E500: Add ESR bit definitions Alexander Graf
2011-08-23 4:55 ` Alexander Graf [this message]
2011-08-23 4:55 ` [Qemu-devel] [PATCH 3/3] PPC: E500: Set ESR values Alexander Graf
2011-08-23 20:34 ` [Qemu-devel] [PATCH 2/3] PPC: E500: Inject SPE exception on invalid SPE access Edgar E. Iglesias
2011-08-23 17:00 ` [Qemu-devel] [PATCH 0/3] PPC: E500: Support SPE guest Jason Wessel
2011-08-23 20:10 ` Edgar E. Iglesias
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1314075344-20839-3-git-send-email-agraf@suse.de \
--to=agraf@suse.de \
--cc=qemu-devel@nongnu.org \
--cc=scottwood@freescale.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).