From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:47182) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QwTfq-0002UG-F2 for qemu-devel@nongnu.org; Thu, 25 Aug 2011 02:44:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QwTfp-00045y-Du for qemu-devel@nongnu.org; Thu, 25 Aug 2011 02:44:22 -0400 Received: from mail-gw0-f45.google.com ([74.125.83.45]:49572) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QwTfp-00042o-BQ for qemu-devel@nongnu.org; Thu, 25 Aug 2011 02:44:21 -0400 Received: by mail-gw0-f45.google.com with SMTP id 19so1694552gwb.4 for ; Wed, 24 Aug 2011 23:44:21 -0700 (PDT) From: "Peter A. G. Crosthwaite" Date: Thu, 25 Aug 2011 16:41:18 +1000 Message-Id: <1314254480-22438-13-git-send-email-peter.crosthwaite@petalogix.com> In-Reply-To: <1314254480-22438-1-git-send-email-peter.crosthwaite@petalogix.com> References: <1314254480-22438-1-git-send-email-peter.crosthwaite@petalogix.com> Subject: [Qemu-devel] [RFC PATCH V1 12/14] microblaze: Make the MSR PVR bit non writable List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, stefanha@linux.vnet.ibm.com, edgar.iglesias@gmail.com, john.williams@petalogix.com, michal.simek@petalogix.com Cc: "Edgar E. Iglesias" From: Edgar E. Iglesias Instead of hardcoding it to 1. Signed-off-by: Edgar E. Iglesias --- target-microblaze/translate.c | 11 ++++++++--- 1 files changed, 8 insertions(+), 3 deletions(-) diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 1a862d3..15f1fe5 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -424,10 +424,15 @@ static inline void msr_read(DisasContext *dc, TCGv d) static inline void msr_write(DisasContext *dc, TCGv v) { + TCGv t; + + t = tcg_temp_new(); dc->cpustate_changed = 1; - tcg_gen_mov_tl(cpu_SR[SR_MSR], v); - /* PVR, we have a processor version register. */ - tcg_gen_ori_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10)); + /* PVR bit is not writable. */ + tcg_gen_andi_tl(t, v, ~(1 << 10)); + tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10)); + tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v); + tcg_temp_free(t); } static void dec_msr(DisasContext *dc) -- 1.7.3.2