* [Qemu-devel] [PATCH 01/19] mips_fulong2e: convert to memory API
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 02/19] mips_jazz: " Avi Kivity
` (17 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/mips_fulong2e.c | 17 ++++++++++-------
1 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c
index ec8c88e..abe3056 100644
--- a/hw/mips_fulong2e.c
+++ b/hw/mips_fulong2e.c
@@ -38,6 +38,7 @@
#include "vt82c686.h"
#include "mc146818rtc.h"
#include "blockdev.h"
+#include "exec-memory.h"
#define DEBUG_FULONG2E_INIT
@@ -256,7 +257,9 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
- unsigned long ram_offset, bios_offset;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *bios = g_new(MemoryRegion, 1);
long bios_size;
int64_t kernel_entry;
qemu_irq *i8259;
@@ -288,12 +291,12 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
bios_size = 1024 * 1024;
/* allocate RAM */
- ram_offset = qemu_ram_alloc(NULL, "fulong2e.ram", ram_size);
- bios_offset = qemu_ram_alloc(NULL, "fulong2e.bios", bios_size);
+ memory_region_init_ram(ram, NULL, "fulong2e.ram", ram_size);
+ memory_region_init_ram(bios, NULL, "fulong2e.bios", bios_size);
+ memory_region_set_readonly(bios, true);
- cpu_register_physical_memory(0, ram_size, ram_offset);
- cpu_register_physical_memory(0x1fc00000LL,
- bios_size, bios_offset | IO_MEM_ROM);
+ memory_region_add_subregion(address_space_mem, 0, ram);
+ memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
/* We do not support flash operation, just loading pmon.bin as raw BIOS.
* Please use -L to set the BIOS path and -bios to set bios name. */
@@ -304,7 +307,7 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
loaderparams.kernel_cmdline = kernel_cmdline;
loaderparams.initrd_filename = initrd_filename;
kernel_entry = load_kernel (env);
- write_bootloader(env, qemu_get_ram_ptr(bios_offset), kernel_entry);
+ write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
} else {
if (bios_name == NULL) {
bios_name = FULONG_BIOSNAME;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 02/19] mips_jazz: convert to memory API
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 01/19] mips_fulong2e: convert to memory API Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 03/19] mips_malta: " Avi Kivity
` (16 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/mips_jazz.c | 81 +++++++++++++++++++++++++++----------------------------
1 files changed, 40 insertions(+), 41 deletions(-)
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index a741086..91e15b9 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -52,44 +52,42 @@ static void main_cpu_reset(void *opaque)
cpu_reset(env);
}
-static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
return cpu_inw(0x71);
}
-static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rtc_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
cpu_outw(0x71, val & 0xff);
}
-static CPUReadMemoryFunc * const rtc_read[3] = {
- rtc_readb,
- rtc_readb,
- rtc_readb,
+static const MemoryRegionOps rtc_ops = {
+ .read = rtc_read,
+ .write = rtc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const rtc_write[3] = {
- rtc_writeb,
- rtc_writeb,
- rtc_writeb,
-};
-
-static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
/* Nothing to do. That is only to ensure that
* the current DMA acknowledge cycle is completed. */
+ return 0xff;
}
-static CPUReadMemoryFunc * const dma_dummy_read[3] = {
- NULL,
- NULL,
- NULL,
-};
+static void dma_dummy_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
+{
+ /* Nothing to do. That is only to ensure that
+ * the current DMA acknowledge cycle is completed. */
+}
-static CPUWriteMemoryFunc * const dma_dummy_write[3] = {
- dma_dummy_writeb,
- dma_dummy_writeb,
- dma_dummy_writeb,
+static const MemoryRegionOps dma_dummy_ops = {
+ .read = dma_dummy_read,
+ .write = dma_dummy_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
#define MAGNUM_BIOS_SIZE_MAX 0x7e000
@@ -105,7 +103,7 @@ static void cpu_request_exit(void *opaque, int irq, int level)
}
static
-void mips_jazz_init (ram_addr_t ram_size,
+void mips_jazz_init (MemoryRegion *address_space, ram_addr_t ram_size,
const char *cpu_model,
enum jazz_model_e jazz_model)
{
@@ -115,7 +113,8 @@ void mips_jazz_init (ram_addr_t ram_size,
qemu_irq *rc4030, *i8259;
rc4030_dma *dmas;
void* rc4030_opaque;
- int s_rtc, s_dma_dummy;
+ MemoryRegion *rtc = g_new(MemoryRegion, 1);
+ MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
NICInfo *nd;
DeviceState *dev;
SysBusDevice *sysbus;
@@ -123,8 +122,9 @@ void mips_jazz_init (ram_addr_t ram_size,
DriveInfo *fds[MAX_FD];
qemu_irq esp_reset, dma_enable;
qemu_irq *cpu_exit_irq;
- ram_addr_t ram_offset;
- ram_addr_t bios_offset;
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *bios = g_new(MemoryRegion, 1);
+ MemoryRegion *bios2 = g_new(MemoryRegion, 1);
/* init CPUs */
if (cpu_model == NULL) {
@@ -143,14 +143,15 @@ void mips_jazz_init (ram_addr_t ram_size,
qemu_register_reset(main_cpu_reset, env);
/* allocate RAM */
- ram_offset = qemu_ram_alloc(NULL, "mips_jazz.ram", ram_size);
- cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
+ memory_region_init_ram(ram, NULL, "mips_jazz.ram", ram_size);
+ memory_region_add_subregion(address_space, 0, ram);
- bios_offset = qemu_ram_alloc(NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
- cpu_register_physical_memory(0x1fc00000LL,
- MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
- cpu_register_physical_memory(0xfff00000LL,
- MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
+ memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
+ memory_region_set_readonly(bios, true);
+ memory_region_init_alias(bios2, "mips_jazz.bios", bios,
+ 0, MAGNUM_BIOS_SIZE);
+ memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
+ memory_region_add_subregion(address_space, 0xfff00000LL, bios);
/* load the BIOS image. */
if (bios_name == NULL)
@@ -175,9 +176,8 @@ void mips_jazz_init (ram_addr_t ram_size,
/* Chipset */
rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
- s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
+ memory_region_init_io(dma_dummy, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
+ memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
/* ISA devices */
i8259 = i8259_init(env->irq[4]);
@@ -240,9 +240,8 @@ void mips_jazz_init (ram_addr_t ram_size,
/* Real time clock */
rtc_init(1980, NULL);
- s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
+ memory_region_init_io(rtc, &rtc_ops, NULL, "rtc", 0x1000);
+ memory_region_add_subregion(address_space, 0x80004000, rtc);
/* Keyboard (i8042) */
i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
@@ -287,7 +286,7 @@ void mips_magnum_init (ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- mips_jazz_init(ram_size, cpu_model, JAZZ_MAGNUM);
+ mips_jazz_init(get_system_memory(), ram_size, cpu_model, JAZZ_MAGNUM);
}
static
@@ -296,7 +295,7 @@ void mips_pica61_init (ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- mips_jazz_init(ram_size, cpu_model, JAZZ_PICA61);
+ mips_jazz_init(get_system_memory(), ram_size, cpu_model, JAZZ_PICA61);
}
static QEMUMachine mips_magnum_machine = {
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 03/19] mips_malta: convert to memory API
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 01/19] mips_fulong2e: convert to memory API Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 02/19] mips_jazz: " Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 04/19] mips_mipssim: " Avi Kivity
` (15 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/mips_malta.c | 53 +++++++++++++++++++++++++++--------------------------
1 files changed, 27 insertions(+), 26 deletions(-)
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index b5c9bcf..a093b65 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -57,6 +57,9 @@
#define MAX_IDE_BUS 2
typedef struct {
+ MemoryRegion iomem;
+ MemoryRegion iomem_lo; /* 0 - 0x900 */
+ MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */
uint32_t leds;
uint32_t brk;
uint32_t gpout;
@@ -215,7 +218,8 @@ static void eeprom24c0x_write(int scl, int sda)
eeprom.sda = sda;
}
-static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t malta_fpga_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
MaltaFPGAState *s = opaque;
uint32_t val = 0;
@@ -302,8 +306,8 @@ static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
return val;
}
-static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void malta_fpga_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
MaltaFPGAState *s = opaque;
uint32_t saddr;
@@ -328,7 +332,7 @@ static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
/* ASCIIWORD Register */
case 0x00410:
- snprintf(s->display_text, 9, "%08X", val);
+ snprintf(s->display_text, 9, "%08X", (uint32_t)val);
malta_fpga_update_display(s);
break;
@@ -388,16 +392,10 @@ static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const malta_fpga_read[] = {
- malta_fpga_readl,
- malta_fpga_readl,
- malta_fpga_readl
-};
-
-static CPUWriteMemoryFunc * const malta_fpga_write[] = {
- malta_fpga_writel,
- malta_fpga_writel,
- malta_fpga_writel
+static const MemoryRegionOps malta_fpga_ops = {
+ .read = malta_fpga_read,
+ .write = malta_fpga_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void malta_fpga_reset(void *opaque)
@@ -429,20 +427,22 @@ static void malta_fpga_led_init(CharDriverState *chr)
qemu_chr_fe_printf(chr, "+--------+\r\n");
}
-static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
+static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
+ target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
{
MaltaFPGAState *s;
- int malta;
s = (MaltaFPGAState *)g_malloc0(sizeof(MaltaFPGAState));
- malta = cpu_register_io_memory(malta_fpga_read,
- malta_fpga_write, s,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem, &malta_fpga_ops, s,
+ "malta-fpga", 0x100000);
+ memory_region_init_alias(&s->iomem_lo, "malta-fpga",
+ &s->iomem, 0, 0x900);
+ memory_region_init_alias(&s->iomem_hi, "malta-fpga",
+ &s->iomem, 0xa00, 0x10000-0xa00);
- cpu_register_physical_memory(base, 0x900, malta);
- /* 0xa00 is less than a page, so will still get the right offsets. */
- cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta);
+ memory_region_add_subregion(address_space, base, &s->iomem_lo);
+ memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
s->display = qemu_chr_new("fpga", "vc:320x200", malta_fpga_led_init);
@@ -762,8 +762,8 @@ void mips_malta_init (ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
- ram_addr_t ram_offset;
MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *bios_1e0 = g_new(MemoryRegion, 1);
MemoryRegion *bios_1fc = g_new(MemoryRegion, 1);
@@ -820,11 +820,11 @@ void mips_malta_init (ram_addr_t ram_size,
bios_ops = &pflash_cfi01_ops_le;
#endif
- ram_offset = qemu_ram_alloc(NULL, "mips_malta.ram", ram_size);
+ memory_region_init_ram(ram, NULL, "mips_malta.ram", ram_size);
memory_region_init_rom_device(bios, bios_ops, NULL,
"mips_malta.bios", BIOS_SIZE);
- cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
+ memory_region_add_subregion(address_space_mem, 0, ram);
/* Map the bios at two physical locations, as on the real board. */
memory_region_init_alias(bios_1e0, "bios-1e0", bios, 0, BIOS_SIZE);
@@ -833,7 +833,8 @@ void mips_malta_init (ram_addr_t ram_size,
memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios_1fc);
/* FPGA */
- malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);
+ malta_fpga_init(address_space_mem, 0x1f000000LL,
+ env->irq[2], serial_hds[2]);
/* Load firmware in flash / BIOS unless we boot directly into a kernel. */
if (kernel_filename) {
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 04/19] mips_mipssim: convert to memory API
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
` (2 preceding siblings ...)
2011-08-25 8:09 ` [Qemu-devel] [PATCH 03/19] mips_malta: " Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 05/19] mips_r4k: " Avi Kivity
` (14 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/mips_mipssim.c | 16 +++++++++-------
1 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c
index 0d46cc4..d013494 100644
--- a/hw/mips_mipssim.c
+++ b/hw/mips_mipssim.c
@@ -35,6 +35,7 @@
#include "mips-bios.h"
#include "loader.h"
#include "elf.h"
+#include "exec-memory.h"
static struct _loaderparams {
int ram_size;
@@ -119,8 +120,9 @@ mips_mipssim_init (ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
- ram_addr_t ram_offset;
- ram_addr_t bios_offset;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *bios = g_new(MemoryRegion, 1);
CPUState *env;
ResetData *reset_info;
int bios_size;
@@ -144,14 +146,14 @@ mips_mipssim_init (ram_addr_t ram_size,
qemu_register_reset(main_cpu_reset, reset_info);
/* Allocate RAM. */
- ram_offset = qemu_ram_alloc(NULL, "mips_mipssim.ram", ram_size);
- bios_offset = qemu_ram_alloc(NULL, "mips_mipssim.bios", BIOS_SIZE);
+ memory_region_init_ram(ram, NULL, "mips_mipssim.ram", ram_size);
+ memory_region_init_ram(bios, NULL, "mips_mipssim.bios", BIOS_SIZE);
+ memory_region_set_readonly(bios, true);
- cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
+ memory_region_add_subregion(address_space_mem, 0, ram);
/* Map the BIOS / boot exception handler. */
- cpu_register_physical_memory(0x1fc00000LL,
- BIOS_SIZE, bios_offset | IO_MEM_ROM);
+ memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
/* Load a BIOS / boot exception handler image. */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 05/19] mips_r4k: convert to memory API
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
` (3 preceding siblings ...)
2011-08-25 8:09 ` [Qemu-devel] [PATCH 04/19] mips_mipssim: " Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 06/19] musicpal: " Avi Kivity
` (13 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/mips_r4k.c | 38 ++++++++++++++------------------------
1 files changed, 14 insertions(+), 24 deletions(-)
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index 51dc868..efa4b05 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -42,8 +42,8 @@ static struct _loaderparams {
const char *initrd_filename;
} loaderparams;
-static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void mips_qemu_write (void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
if ((addr & 0xffff) == 0 && val == 42)
qemu_system_reset_request ();
@@ -51,25 +51,18 @@ static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
qemu_system_shutdown_request ();
}
-static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t mips_qemu_read (void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
return 0;
}
-static CPUWriteMemoryFunc * const mips_qemu_write[] = {
- &mips_qemu_writel,
- &mips_qemu_writel,
- &mips_qemu_writel,
+static const MemoryRegionOps mips_qemu_ops = {
+ .read = mips_qemu_read,
+ .write = mips_qemu_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUReadMemoryFunc * const mips_qemu_read[] = {
- &mips_qemu_readl,
- &mips_qemu_readl,
- &mips_qemu_readl,
-};
-
-static int mips_qemu_iomemtype = 0;
-
typedef struct ResetData {
CPUState *env;
uint64_t vector;
@@ -163,9 +156,10 @@ void mips_r4k_init (ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
- ram_addr_t ram_offset;
MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
+ MemoryRegion *iomem = g_new(MemoryRegion, 1);
int bios_size;
CPUState *env;
ResetData *reset_info;
@@ -200,16 +194,12 @@ void mips_r4k_init (ram_addr_t ram_size,
((unsigned int)ram_size / (1 << 20)));
exit(1);
}
- ram_offset = qemu_ram_alloc(NULL, "mips_r4k.ram", ram_size);
+ memory_region_init_ram(ram, NULL, "mips_r4k.ram", ram_size);
- cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
+ memory_region_add_subregion(address_space_mem, 0, ram);
- if (!mips_qemu_iomemtype) {
- mips_qemu_iomemtype = cpu_register_io_memory(mips_qemu_read,
- mips_qemu_write, NULL,
- DEVICE_NATIVE_ENDIAN);
- }
- cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
+ memory_region_init_io(iomem, &mips_qemu_ops, NULL, "mips-qemu", 0x10000);
+ memory_region_add_subregion(address_space_mem, 0x1fbf0000, iomem);
/* Try to load a BIOS image. If this fails, we continue regardless,
but initialize the hardware ourselves. When a kernel gets
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 06/19] musicpal: convert to memory API
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
` (4 preceding siblings ...)
2011-08-25 8:09 ` [Qemu-devel] [PATCH 05/19] mips_r4k: " Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 07/19] omap1: convert to memory API (part I) Avi Kivity
` (12 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/musicpal.c | 243 +++++++++++++++++++++++----------------------------------
1 files changed, 99 insertions(+), 144 deletions(-)
diff --git a/hw/musicpal.c b/hw/musicpal.c
index 5e74ee7..ffde117 100644
--- a/hw/musicpal.c
+++ b/hw/musicpal.c
@@ -19,6 +19,7 @@
#include "console.h"
#include "i2c.h"
#include "blockdev.h"
+#include "exec-memory.h"
#define MP_MISC_BASE 0x80002000
#define MP_MISC_SIZE 0x00001000
@@ -142,6 +143,7 @@ typedef struct mv88w8618_rx_desc {
typedef struct mv88w8618_eth_state {
SysBusDevice busdev;
+ MemoryRegion iomem;
qemu_irq irq;
uint32_t smir;
uint32_t icr;
@@ -260,7 +262,8 @@ static void eth_send(mv88w8618_eth_state *s, int queue_index)
} while (desc_addr != s->tx_queue[queue_index]);
}
-static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
+static uint64_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
mv88w8618_eth_state *s = opaque;
@@ -302,7 +305,7 @@ static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
}
static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
mv88w8618_eth_state *s = opaque;
@@ -353,16 +356,10 @@ static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = {
- mv88w8618_eth_read,
- mv88w8618_eth_read,
- mv88w8618_eth_read
-};
-
-static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = {
- mv88w8618_eth_write,
- mv88w8618_eth_write,
- mv88w8618_eth_write
+static const MemoryRegionOps mv88w8618_eth_ops = {
+ .read = mv88w8618_eth_read,
+ .write = mv88w8618_eth_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void eth_cleanup(VLANClientState *nc)
@@ -387,10 +384,9 @@ static int mv88w8618_eth_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
dev->qdev.info->name, dev->qdev.id, s);
- s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn,
- mv88w8618_eth_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index);
+ memory_region_init_io(&s->iomem, &mv88w8618_eth_ops, s, "mv88w8618-eth",
+ MP_ETH_SIZE);
+ sysbus_init_mmio_region(dev, &s->iomem);
return 0;
}
@@ -444,6 +440,7 @@ static SysBusDeviceInfo mv88w8618_eth_info = {
typedef struct musicpal_lcd_state {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t brightness;
uint32_t mode;
uint32_t irqctrl;
@@ -528,7 +525,8 @@ static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
s->brightness |= level << irq;
}
-static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
+static uint64_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
musicpal_lcd_state *s = opaque;
@@ -542,7 +540,7 @@ static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
}
static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
musicpal_lcd_state *s = opaque;
@@ -581,29 +579,21 @@ static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = {
- musicpal_lcd_read,
- musicpal_lcd_read,
- musicpal_lcd_read
-};
-
-static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = {
- musicpal_lcd_write,
- musicpal_lcd_write,
- musicpal_lcd_write
+static const MemoryRegionOps musicpal_lcd_ops = {
+ .read = musicpal_lcd_read,
+ .write = musicpal_lcd_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int musicpal_lcd_init(SysBusDevice *dev)
{
musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
- int iomemtype;
s->brightness = 7;
- iomemtype = cpu_register_io_memory(musicpal_lcd_readfn,
- musicpal_lcd_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);
+ memory_region_init_io(&s->iomem, &musicpal_lcd_ops, s,
+ "musicpal-lcd", MP_LCD_SIZE);
+ sysbus_init_mmio_region(dev, &s->iomem);
s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
NULL, NULL, s);
@@ -645,6 +635,7 @@ static SysBusDeviceInfo musicpal_lcd_info = {
typedef struct mv88w8618_pic_state
{
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t level;
uint32_t enabled;
qemu_irq parent_irq;
@@ -667,7 +658,8 @@ static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
mv88w8618_pic_update(s);
}
-static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
+static uint64_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
mv88w8618_pic_state *s = opaque;
@@ -681,7 +673,7 @@ static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
}
static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
mv88w8618_pic_state *s = opaque;
@@ -707,29 +699,21 @@ static void mv88w8618_pic_reset(DeviceState *d)
s->enabled = 0;
}
-static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = {
- mv88w8618_pic_read,
- mv88w8618_pic_read,
- mv88w8618_pic_read
-};
-
-static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = {
- mv88w8618_pic_write,
- mv88w8618_pic_write,
- mv88w8618_pic_write
+static const MemoryRegionOps mv88w8618_pic_ops = {
+ .read = mv88w8618_pic_read,
+ .write = mv88w8618_pic_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int mv88w8618_pic_init(SysBusDevice *dev)
{
mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
- int iomemtype;
qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
sysbus_init_irq(dev, &s->parent_irq);
- iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn,
- mv88w8618_pic_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
+ memory_region_init_io(&s->iomem, &mv88w8618_pic_ops, s,
+ "musicpal-pic", MP_PIC_SIZE);
+ sysbus_init_mmio_region(dev, &s->iomem);
return 0;
}
@@ -775,6 +759,7 @@ typedef struct mv88w8618_timer_state {
typedef struct mv88w8618_pit_state {
SysBusDevice busdev;
+ MemoryRegion iomem;
mv88w8618_timer_state timer[4];
} mv88w8618_pit_state;
@@ -797,7 +782,8 @@ static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
s->ptimer = ptimer_init(bh);
}
-static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
+static uint64_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
mv88w8618_pit_state *s = opaque;
mv88w8618_timer_state *t;
@@ -813,7 +799,7 @@ static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
}
static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
mv88w8618_pit_state *s = opaque;
mv88w8618_timer_state *t;
@@ -864,21 +850,14 @@ static void mv88w8618_pit_reset(DeviceState *d)
}
}
-static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = {
- mv88w8618_pit_read,
- mv88w8618_pit_read,
- mv88w8618_pit_read
-};
-
-static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = {
- mv88w8618_pit_write,
- mv88w8618_pit_write,
- mv88w8618_pit_write
+static const MemoryRegionOps mv88w8618_pit_ops = {
+ .read = mv88w8618_pit_read,
+ .write = mv88w8618_pit_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int mv88w8618_pit_init(SysBusDevice *dev)
{
- int iomemtype;
mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
int i;
@@ -888,10 +867,9 @@ static int mv88w8618_pit_init(SysBusDevice *dev)
mv88w8618_timer_init(dev, &s->timer[i], 1000000);
}
- iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn,
- mv88w8618_pit_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype);
+ memory_region_init_io(&s->iomem, &mv88w8618_pit_ops, s,
+ "musicpal-pit", MP_PIT_SIZE);
+ sysbus_init_mmio_region(dev, &s->iomem);
return 0;
}
@@ -932,11 +910,13 @@ static SysBusDeviceInfo mv88w8618_pit_info = {
typedef struct mv88w8618_flashcfg_state {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t cfgr0;
} mv88w8618_flashcfg_state;
-static uint32_t mv88w8618_flashcfg_read(void *opaque,
- target_phys_addr_t offset)
+static uint64_t mv88w8618_flashcfg_read(void *opaque,
+ target_phys_addr_t offset,
+ unsigned size)
{
mv88w8618_flashcfg_state *s = opaque;
@@ -950,7 +930,7 @@ static uint32_t mv88w8618_flashcfg_read(void *opaque,
}
static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
mv88w8618_flashcfg_state *s = opaque;
@@ -961,28 +941,20 @@ static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = {
- mv88w8618_flashcfg_read,
- mv88w8618_flashcfg_read,
- mv88w8618_flashcfg_read
-};
-
-static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = {
- mv88w8618_flashcfg_write,
- mv88w8618_flashcfg_write,
- mv88w8618_flashcfg_write
+static const MemoryRegionOps mv88w8618_flashcfg_ops = {
+ .read = mv88w8618_flashcfg_read,
+ .write = mv88w8618_flashcfg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int mv88w8618_flashcfg_init(SysBusDevice *dev)
{
- int iomemtype;
mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
- iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn,
- mv88w8618_flashcfg_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype);
+ memory_region_init_io(&s->iomem, &mv88w8618_flashcfg_ops, s,
+ "musicpal-flashcfg", MP_FLASHCFG_SIZE);
+ sysbus_init_mmio_region(dev, &s->iomem);
return 0;
}
@@ -1009,7 +981,8 @@ static SysBusDeviceInfo mv88w8618_flashcfg_info = {
#define MP_BOARD_REVISION 0x31
-static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
+static uint64_t musicpal_misc_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
switch (offset) {
case MP_MISC_BOARD_REVISION:
@@ -1021,37 +994,31 @@ static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
}
static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
}
-static CPUReadMemoryFunc * const musicpal_misc_readfn[] = {
- musicpal_misc_read,
- musicpal_misc_read,
- musicpal_misc_read,
-};
-
-static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = {
- musicpal_misc_write,
- musicpal_misc_write,
- musicpal_misc_write,
+static const MemoryRegionOps musicpal_misc_ops = {
+ .read = musicpal_misc_read,
+ .write = musicpal_misc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static void musicpal_misc_init(void)
+static void musicpal_misc_init(SysBusDevice *dev)
{
- int iomemtype;
+ MemoryRegion *iomem = g_new(MemoryRegion, 1);
- iomemtype = cpu_register_io_memory(musicpal_misc_readfn,
- musicpal_misc_writefn, NULL,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
+ memory_region_init_io(iomem, &musicpal_misc_ops, NULL,
+ "musicpal-misc", MP_MISC_SIZE);
+ sysbus_add_memory(dev, MP_MISC_BASE, iomem);
}
/* WLAN register offsets */
#define MP_WLAN_MAGIC1 0x11c
#define MP_WLAN_MAGIC2 0x124
-static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
+static uint64_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
switch (offset) {
/* Workaround to allow loading the binary-only wlandrv.ko crap
@@ -1067,30 +1034,23 @@ static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
}
static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
}
-static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = {
- mv88w8618_wlan_read,
- mv88w8618_wlan_read,
- mv88w8618_wlan_read,
-};
-
-static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = {
- mv88w8618_wlan_write,
- mv88w8618_wlan_write,
- mv88w8618_wlan_write,
+static const MemoryRegionOps mv88w8618_wlan_ops = {
+ .read = mv88w8618_wlan_read,
+ .write =mv88w8618_wlan_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int mv88w8618_wlan_init(SysBusDevice *dev)
{
- int iomemtype;
+ MemoryRegion *iomem = g_new(MemoryRegion, 1);
- iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn,
- mv88w8618_wlan_writefn, NULL,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype);
+ memory_region_init_io(iomem, &mv88w8618_wlan_ops, NULL,
+ "musicpal-wlan", MP_WLAN_SIZE);
+ sysbus_init_mmio_region(dev, iomem);
return 0;
}
@@ -1118,6 +1078,7 @@ static int mv88w8618_wlan_init(SysBusDevice *dev)
typedef struct musicpal_gpio_state {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t lcd_brightness;
uint32_t out_state;
uint32_t in_state;
@@ -1190,7 +1151,8 @@ static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
}
}
-static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
+static uint64_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
musicpal_gpio_state *s = opaque;
@@ -1229,7 +1191,7 @@ static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
}
static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
musicpal_gpio_state *s = opaque;
switch (offset) {
@@ -1267,16 +1229,10 @@ static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = {
- musicpal_gpio_read,
- musicpal_gpio_read,
- musicpal_gpio_read,
-};
-
-static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = {
- musicpal_gpio_write,
- musicpal_gpio_write,
- musicpal_gpio_write,
+static const MemoryRegionOps musicpal_gpio_ops = {
+ .read = musicpal_gpio_read,
+ .write = musicpal_gpio_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void musicpal_gpio_reset(DeviceState *d)
@@ -1295,14 +1251,12 @@ static void musicpal_gpio_reset(DeviceState *d)
static int musicpal_gpio_init(SysBusDevice *dev)
{
musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
- int iomemtype;
sysbus_init_irq(dev, &s->irq);
- iomemtype = cpu_register_io_memory(musicpal_gpio_readfn,
- musicpal_gpio_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype);
+ memory_region_init_io(&s->iomem, &musicpal_gpio_ops, s,
+ "musicpal-gpio", MP_GPIO_SIZE);
+ sysbus_init_mmio_region(dev, &s->iomem);
qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
@@ -1501,7 +1455,9 @@ static void musicpal_init(ram_addr_t ram_size,
int i;
unsigned long flash_size;
DriveInfo *dinfo;
- ram_addr_t sram_off;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *sram = g_new(MemoryRegion, 1);
MemoryRegion *flash = g_new(MemoryRegion, 1);
if (!cpu_model) {
@@ -1515,12 +1471,11 @@ static void musicpal_init(ram_addr_t ram_size,
cpu_pic = arm_pic_init_cpu(env);
/* For now we use a fixed - the original - RAM size */
- cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
- qemu_ram_alloc(NULL, "musicpal.ram",
- MP_RAM_DEFAULT_SIZE));
+ memory_region_init_ram(ram, NULL, "musicpal.ram", MP_RAM_DEFAULT_SIZE);
+ memory_region_add_subregion(address_space_mem, 0, ram);
- sram_off = qemu_ram_alloc(NULL, "musicpal.sram", MP_SRAM_SIZE);
- cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
+ memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE);
+ memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
cpu_pic[ARM_PIC_CPU_IRQ]);
@@ -1597,7 +1552,7 @@ static void musicpal_init(ram_addr_t ram_size,
sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
- musicpal_misc_init();
+ musicpal_misc_init(sysbus_from_qdev(dev));
dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 07/19] omap1: convert to memory API (part I)
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
` (5 preceding siblings ...)
2011-08-25 8:09 ` [Qemu-devel] [PATCH 06/19] musicpal: " Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 08/19] omap1: convert to memory API (part II) Avi Kivity
` (11 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/omap.h | 11 ++-
hw/omap1.c | 338 +++++++++++++++++++++++++++++++-------------------------
hw/omap_sx1.c | 4 +-
hw/palm.c | 4 +-
4 files changed, 203 insertions(+), 154 deletions(-)
diff --git a/hw/omap.h b/hw/omap.h
index db101c6..bae6bed 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -822,6 +822,14 @@ struct omap_mpu_state_s {
qemu_irq wakeup;
+ MemoryRegion ulpd_pm_iomem;
+ MemoryRegion pin_cfg_iomem;
+ MemoryRegion id_iomem;
+ MemoryRegion id_iomem_e18;
+ MemoryRegion id_iomem_ed4;
+ MemoryRegion id_iomem_e20;
+ MemoryRegion mpui_iomem;
+
struct omap_dma_port_if_s {
uint32_t (*read[3])(struct omap_mpu_state_s *s,
target_phys_addr_t offset);
@@ -943,7 +951,8 @@ struct omap_mpu_state_s {
};
/* omap1.c */
-struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
+struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
+ unsigned long sdram_size,
const char *core);
/* omap2.c */
diff --git a/hw/omap1.c b/hw/omap1.c
index 614fd31..0f7e14f 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -84,6 +84,7 @@ void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
/* MPU OS timers */
struct omap_mpu_timer_s {
+ MemoryRegion iomem;
qemu_irq irq;
omap_clk clk;
uint32_t val;
@@ -179,10 +180,15 @@ static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
timer->rate = omap_clk_getrate(timer->clk);
}
-static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* CNTL_TIMER */
return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
@@ -199,10 +205,14 @@ static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
}
static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* CNTL_TIMER */
omap_timer_sync(s);
@@ -226,16 +236,10 @@ static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_mpu_timer_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_mpu_timer_read,
-};
-
-static CPUWriteMemoryFunc * const omap_mpu_timer_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_mpu_timer_write,
+static const MemoryRegionOps omap_mpu_timer_ops = {
+ .read = omap_mpu_timer_read,
+ .write = omap_mpu_timer_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
@@ -250,10 +254,10 @@ static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
s->it_ena = 1;
}
-static struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
+static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
qemu_irq irq, omap_clk clk)
{
- int iomemtype;
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
g_malloc0(sizeof(struct omap_mpu_timer_s));
@@ -264,9 +268,10 @@ static struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
omap_mpu_timer_reset(s);
omap_timer_clk_setup(s);
- iomemtype = cpu_register_io_memory(omap_mpu_timer_readfn,
- omap_mpu_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x100, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_mpu_timer_ops, s,
+ "omap-mpu-timer", 0x100);
+
+ memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
}
@@ -274,16 +279,22 @@ static struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
/* Watchdog timer */
struct omap_watchdog_timer_s {
struct omap_mpu_timer_s timer;
+ MemoryRegion iomem;
uint8_t last_wr;
int mode;
int free;
int reset;
};
-static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* CNTL_TIMER */
return (s->timer.ptv << 9) | (s->timer.ar << 8) |
@@ -301,10 +312,14 @@ static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
}
static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* CNTL_TIMER */
omap_timer_sync(&s->timer);
@@ -344,16 +359,10 @@ static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_wd_timer_readfn[] = {
- omap_badwidth_read16,
- omap_wd_timer_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_wd_timer_writefn[] = {
- omap_badwidth_write16,
- omap_wd_timer_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_wd_timer_ops = {
+ .read = omap_wd_timer_read,
+ .write = omap_wd_timer_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
@@ -374,10 +383,10 @@ static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
omap_timer_update(&s->timer);
}
-static struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
+static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
+ target_phys_addr_t base,
qemu_irq irq, omap_clk clk)
{
- int iomemtype;
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
g_malloc0(sizeof(struct omap_watchdog_timer_s));
@@ -387,9 +396,9 @@ static struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
omap_wd_timer_reset(s);
omap_timer_clk_setup(&s->timer);
- iomemtype = cpu_register_io_memory(omap_wd_timer_readfn,
- omap_wd_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x100, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_wd_timer_ops, s,
+ "omap-wd-timer", 0x100);
+ memory_region_add_subregion(memory, base, &s->iomem);
return s;
}
@@ -397,13 +406,19 @@ static struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
/* 32-kHz timer */
struct omap_32khz_timer_s {
struct omap_mpu_timer_s timer;
+ MemoryRegion iomem;
};
-static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* TVR */
return s->timer.reset_val;
@@ -422,11 +437,15 @@ static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
}
static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (offset) {
case 0x00: /* TVR */
s->timer.reset_val = value & 0x00ffffff;
@@ -452,16 +471,10 @@ static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_os_timer_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_os_timer_read,
-};
-
-static CPUWriteMemoryFunc * const omap_os_timer_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_os_timer_write,
+static const MemoryRegionOps omap_os_timer_ops = {
+ .read = omap_os_timer_read,
+ .write = omap_os_timer_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
@@ -476,10 +489,10 @@ static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
s->timer.ar = 1;
}
-static struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
+static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
+ target_phys_addr_t base,
qemu_irq irq, omap_clk clk)
{
- int iomemtype;
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
g_malloc0(sizeof(struct omap_32khz_timer_s));
@@ -489,19 +502,24 @@ static struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
omap_os_timer_reset(s);
omap_timer_clk_setup(&s->timer);
- iomemtype = cpu_register_io_memory(omap_os_timer_readfn,
- omap_os_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_os_timer_ops, s,
+ "omap-os-timer", 0x800);
+ memory_region_add_subregion(memory, base, &s->iomem);
return s;
}
/* Ultra Low-Power Device Module */
-static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint16_t ret;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (addr) {
case 0x14: /* IT_STATUS */
ret = s->ulpd_pm_regs[addr >> 2];
@@ -560,7 +578,7 @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
}
static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int64_t now, ticks;
@@ -568,6 +586,10 @@ static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
static const int bypass_div[4] = { 1, 2, 4, 4 };
uint16_t diff;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* COUNTER_32_LSB */
case 0x04: /* COUNTER_32_MSB */
@@ -674,16 +696,10 @@ static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_ulpd_pm_readfn[] = {
- omap_badwidth_read16,
- omap_ulpd_pm_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_ulpd_pm_writefn[] = {
- omap_badwidth_write16,
- omap_ulpd_pm_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_ulpd_pm_ops = {
+ .read = omap_ulpd_pm_read,
+ .write = omap_ulpd_pm_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
@@ -713,21 +729,26 @@ static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
}
-static void omap_ulpd_pm_init(target_phys_addr_t base,
+static void omap_ulpd_pm_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
- int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn,
- omap_ulpd_pm_writefn, mpu, DEVICE_NATIVE_ENDIAN);
-
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&mpu->ulpd_pm_iomem, &omap_ulpd_pm_ops, mpu,
+ "omap-ulpd-pm", 0x800);
+ memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem);
omap_ulpd_pm_reset(mpu);
}
/* OMAP Pin Configuration */
-static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* FUNC_MUX_CTRL_0 */
case 0x04: /* FUNC_MUX_CTRL_1 */
@@ -827,11 +848,15 @@ static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
}
static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint32_t diff;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* FUNC_MUX_CTRL_0 */
diff = s->func_mux_ctrl[addr >> 2] ^ value;
@@ -900,16 +925,10 @@ static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_pin_cfg_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_pin_cfg_read,
-};
-
-static CPUWriteMemoryFunc * const omap_pin_cfg_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_pin_cfg_write,
+static const MemoryRegionOps omap_pin_cfg_ops = {
+ .read = omap_pin_cfg_read,
+ .write = omap_pin_cfg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
@@ -928,21 +947,26 @@ static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
}
-static void omap_pin_cfg_init(target_phys_addr_t base,
+static void omap_pin_cfg_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
- int iomemtype = cpu_register_io_memory(omap_pin_cfg_readfn,
- omap_pin_cfg_writefn, mpu, DEVICE_NATIVE_ENDIAN);
-
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu,
+ "omap-pin-cfg", 0x800);
+ memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem);
omap_pin_cfg_reset(mpu);
}
/* Device Identification, Die Identification */
-static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_id_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0xfffe1800: /* DIE_ID_LSB */
return 0xc9581f0e;
@@ -982,38 +1006,48 @@ static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
}
static void omap_id_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
OMAP_BAD_REG(addr);
}
-static CPUReadMemoryFunc * const omap_id_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_id_read,
-};
-
-static CPUWriteMemoryFunc * const omap_id_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_id_write,
+static const MemoryRegionOps omap_id_ops = {
+ .read = omap_id_read,
+ .write = omap_id_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static void omap_id_init(struct omap_mpu_state_s *mpu)
+static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
{
- int iomemtype = cpu_register_io_memory(omap_id_readfn,
- omap_id_writefn, mpu, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800);
- cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400);
- if (!cpu_is_omap15xx(mpu))
- cpu_register_physical_memory_offset(0xfffe2000, 0x800, iomemtype, 0xfffe2000);
+ memory_region_init_io(&mpu->id_iomem, &omap_id_ops, mpu,
+ "omap-id", 0x100000000ULL);
+ memory_region_init_alias(&mpu->id_iomem_e18, "omap-id-e18", &mpu->id_iomem,
+ 0xfffe1800, 0x800);
+ memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18);
+ memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-ed4", &mpu->id_iomem,
+ 0xfffed400, 0x100);
+ memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4);
+ if (!cpu_is_omap15xx(mpu)) {
+ memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-e20",
+ &mpu->id_iomem, 0xfffe2000, 0x800);
+ memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20);
+ }
}
/* MPUI Control (Dummy) */
-static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_mpui_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* CTRL */
return s->mpui_ctrl;
@@ -1039,10 +1073,14 @@ static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
}
static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* CTRL */
s->mpui_ctrl = value & 0x007fffff;
@@ -1064,16 +1102,10 @@ static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_mpui_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_mpui_read,
-};
-
-static CPUWriteMemoryFunc * const omap_mpui_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_mpui_write,
+static const MemoryRegionOps omap_mpui_ops = {
+ .read = omap_mpui_read,
+ .write = omap_mpui_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_mpui_reset(struct omap_mpu_state_s *s)
@@ -1081,13 +1113,12 @@ static void omap_mpui_reset(struct omap_mpu_state_s *s)
s->mpui_ctrl = 0x0003ff1b;
}
-static void omap_mpui_init(target_phys_addr_t base,
+static void omap_mpui_init(MemoryRegion *memory, target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
- int iomemtype = cpu_register_io_memory(omap_mpui_readfn,
- omap_mpui_writefn, mpu, DEVICE_NATIVE_ENDIAN);
-
- cpu_register_physical_memory(base, 0x100, iomemtype);
+ memory_region_init_io(&mpu->mpui_iomem, &omap_mpui_ops, mpu,
+ "omap-mpui", 0x100);
+ memory_region_add_subregion(memory, base, &mpu->mpui_iomem);
omap_mpui_reset(mpu);
}
@@ -1095,6 +1126,7 @@ static void omap_mpui_init(target_phys_addr_t base,
/* TIPB Bridges */
struct omap_tipb_bridge_s {
qemu_irq abort;
+ MemoryRegion iomem;
int width_intr;
uint16_t control;
@@ -1103,10 +1135,15 @@ struct omap_tipb_bridge_s {
uint16_t enh_control;
};
-static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
+ if (size < 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* TIPB_CNTL */
return s->control;
@@ -1129,10 +1166,14 @@ static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
}
static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
+ if (size < 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* TIPB_CNTL */
s->control = value & 0xffff;
@@ -1163,16 +1204,10 @@ static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_tipb_bridge_readfn[] = {
- omap_badwidth_read16,
- omap_tipb_bridge_read,
- omap_tipb_bridge_read,
-};
-
-static CPUWriteMemoryFunc * const omap_tipb_bridge_writefn[] = {
- omap_badwidth_write16,
- omap_tipb_bridge_write,
- omap_tipb_bridge_write,
+static const MemoryRegionOps omap_tipb_bridge_ops = {
+ .read = omap_tipb_bridge_read,
+ .write = omap_tipb_bridge_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
@@ -1183,19 +1218,19 @@ static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
s->enh_control = 0x000f;
}
-static struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
- qemu_irq abort_irq, omap_clk clk)
+static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
+ MemoryRegion *memory, target_phys_addr_t base,
+ qemu_irq abort_irq, omap_clk clk)
{
- int iomemtype;
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
g_malloc0(sizeof(struct omap_tipb_bridge_s));
s->abort = abort_irq;
omap_tipb_bridge_reset(s);
- iomemtype = cpu_register_io_memory(omap_tipb_bridge_readfn,
- omap_tipb_bridge_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x100, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_tipb_bridge_ops, s,
+ "omap-tipb-bridge", 0x100);
+ memory_region_add_subregion(memory, base, &s->iomem);
return s;
}
@@ -3706,7 +3741,8 @@ static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
}
-struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
+struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
+ unsigned long sdram_size,
const char *core)
{
int i;
@@ -3772,21 +3808,21 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
soc_dma_port_add_mem_ram(s->dma,
imif_base, OMAP_IMIF_BASE, s->sram_size);
- s->timer[0] = omap_mpu_timer_init(0xfffec500,
+ s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500,
s->irq[0][OMAP_INT_TIMER1],
omap_findclk(s, "mputim_ck"));
- s->timer[1] = omap_mpu_timer_init(0xfffec600,
+ s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600,
s->irq[0][OMAP_INT_TIMER2],
omap_findclk(s, "mputim_ck"));
- s->timer[2] = omap_mpu_timer_init(0xfffec700,
+ s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700,
s->irq[0][OMAP_INT_TIMER3],
omap_findclk(s, "mputim_ck"));
- s->wdt = omap_wd_timer_init(0xfffec800,
+ s->wdt = omap_wd_timer_init(system_memory, 0xfffec800,
s->irq[0][OMAP_INT_WD_TIMER],
omap_findclk(s, "armwdt_ck"));
- s->os_timer = omap_os_timer_init(0xfffb9000,
+ s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000,
s->irq[1][OMAP_INT_OS_TIMER],
omap_findclk(s, "clk32-kHz"));
@@ -3794,16 +3830,16 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
omap_dma_get_lcdch(s->dma), imif_base, emiff_base,
omap_findclk(s, "lcd_ck"));
- omap_ulpd_pm_init(0xfffe0800, s);
- omap_pin_cfg_init(0xfffe1000, s);
- omap_id_init(s);
+ omap_ulpd_pm_init(system_memory, 0xfffe0800, s);
+ omap_pin_cfg_init(system_memory, 0xfffe1000, s);
+ omap_id_init(system_memory, s);
- omap_mpui_init(0xfffec900, s);
+ omap_mpui_init(system_memory, 0xfffec900, s);
- s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
+ s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00,
s->irq[0][OMAP_INT_BRIDGE_PRIV],
omap_findclk(s, "tipb_ck"));
- s->public_tipb = omap_tipb_bridge_init(0xfffed300,
+ s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300,
s->irq[0][OMAP_INT_BRIDGE_PUB],
omap_findclk(s, "tipb_ck"));
diff --git a/hw/omap_sx1.c b/hw/omap_sx1.c
index 70364f4..0db5dff 100644
--- a/hw/omap_sx1.c
+++ b/hw/omap_sx1.c
@@ -32,6 +32,7 @@
#include "arm-misc.h"
#include "flash.h"
#include "blockdev.h"
+#include "exec-memory.h"
/*****************************************************************************/
/* Siemens SX1 Cellphone V1 */
@@ -121,6 +122,7 @@ static void sx1_init(ram_addr_t ram_size,
const int version)
{
struct omap_mpu_state_s *cpu;
+ MemoryRegion *address_space = get_system_memory();
int io;
static uint32_t cs0val = 0x00213090;
static uint32_t cs1val = 0x00215070;
@@ -136,7 +138,7 @@ static void sx1_init(ram_addr_t ram_size,
flash_size = flash2_size;
}
- cpu = omap310_mpu_init(sx1_binfo.ram_size, cpu_model);
+ cpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, cpu_model);
/* External Flash (EMIFS) */
cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,
diff --git a/hw/palm.c b/hw/palm.c
index 4c67e75..d8f50e3 100644
--- a/hw/palm.c
+++ b/hw/palm.c
@@ -25,6 +25,7 @@
#include "arm-misc.h"
#include "devices.h"
#include "loader.h"
+#include "exec-memory.h"
static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
{
@@ -198,6 +199,7 @@ static void palmte_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
+ MemoryRegion *address_space_mem = get_system_memory();
struct omap_mpu_state_s *cpu;
int flash_size = 0x00800000;
int sdram_size = palmte_binfo.ram_size;
@@ -209,7 +211,7 @@ static void palmte_init(ram_addr_t ram_size,
int rom_size, rom_loaded = 0;
DisplayState *ds = get_displaystate();
- cpu = omap310_mpu_init(sdram_size, cpu_model);
+ cpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model);
/* External Flash (EMIFS) */
cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 08/19] omap1: convert to memory API (part II)
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
` (6 preceding siblings ...)
2011-08-25 8:09 ` [Qemu-devel] [PATCH 07/19] omap1: convert to memory API (part I) Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 09/19] pci: add pci_address_space_io() Avi Kivity
` (10 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/omap.h | 7 ++-
hw/omap1.c | 195 ++++++++++++++++++++++++++++++++----------------------------
2 files changed, 111 insertions(+), 91 deletions(-)
diff --git a/hw/omap.h b/hw/omap.h
index bae6bed..bb25754 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -677,7 +677,8 @@ void omap_uart_reset(struct omap_uart_s *s);
void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
struct omap_mpuio_s;
-struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
+struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk);
qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
@@ -829,6 +830,9 @@ struct omap_mpu_state_s {
MemoryRegion id_iomem_ed4;
MemoryRegion id_iomem_e20;
MemoryRegion mpui_iomem;
+ MemoryRegion tcmi_iomem;
+ MemoryRegion clkm_iomem;
+ MemoryRegion clkdsp_iomem;
struct omap_dma_port_if_s {
uint32_t (*read[3])(struct omap_mpu_state_s *s,
@@ -911,6 +915,7 @@ struct omap_mpu_state_s {
uint32_t tcmi_regs[17];
struct dpll_ctl_s {
+ MemoryRegion iomem;
uint16_t mode;
omap_clk dpll;
} dpll[3];
diff --git a/hw/omap1.c b/hw/omap1.c
index 0f7e14f..05e38fc 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -1236,11 +1236,16 @@ static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
}
/* Dummy Traffic Controller's Memory Interface */
-static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_tcmi_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint32_t ret;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* IMIF_PRIO */
case 0x04: /* EMIFS_PRIO */
@@ -1270,10 +1275,14 @@ static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
}
static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* IMIF_PRIO */
case 0x04: /* EMIFS_PRIO */
@@ -1300,16 +1309,10 @@ static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_tcmi_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_tcmi_read,
-};
-
-static CPUWriteMemoryFunc * const omap_tcmi_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_tcmi_write,
+static const MemoryRegionOps omap_tcmi_ops = {
+ .read = omap_tcmi_read,
+ .write = omap_tcmi_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
@@ -1331,21 +1334,25 @@ static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
}
-static void omap_tcmi_init(target_phys_addr_t base,
+static void omap_tcmi_init(MemoryRegion *memory, target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
- int iomemtype = cpu_register_io_memory(omap_tcmi_readfn,
- omap_tcmi_writefn, mpu, DEVICE_NATIVE_ENDIAN);
-
- cpu_register_physical_memory(base, 0x100, iomemtype);
+ memory_region_init_io(&mpu->tcmi_iomem, &omap_tcmi_ops, mpu,
+ "omap-tcmi", 0x100);
+ memory_region_add_subregion(memory, base, &mpu->tcmi_iomem);
omap_tcmi_reset(mpu);
}
/* Digital phase-locked loops control */
-static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_dpll_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
if (addr == 0x00) /* CTL_REG */
return s->mode;
@@ -1354,13 +1361,17 @@ static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
}
static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
uint16_t diff;
static const int bypass_div[4] = { 1, 2, 4, 4 };
int div, mult;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
if (addr == 0x00) { /* CTL_REG */
/* See omap_ulpd_pm_write() too */
diff = s->mode & value;
@@ -1386,16 +1397,10 @@ static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_dpll_readfn[] = {
- omap_badwidth_read16,
- omap_dpll_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_dpll_writefn[] = {
- omap_badwidth_write16,
- omap_dpll_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_dpll_ops = {
+ .read = omap_dpll_read,
+ .write = omap_dpll_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_dpll_reset(struct dpll_ctl_s *s)
@@ -1404,23 +1409,27 @@ static void omap_dpll_reset(struct dpll_ctl_s *s)
omap_clk_setrate(s->dpll, 1, 1);
}
-static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
- omap_clk clk)
+static void omap_dpll_init(MemoryRegion *memory, struct dpll_ctl_s *s,
+ target_phys_addr_t base, omap_clk clk)
{
- int iomemtype = cpu_register_io_memory(omap_dpll_readfn,
- omap_dpll_writefn, s, DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem, &omap_dpll_ops, s, "omap-dpll", 0x100);
s->dpll = clk;
omap_dpll_reset(s);
- cpu_register_physical_memory(base, 0x100, iomemtype);
+ memory_region_add_subregion(memory, base, &s->iomem);
}
/* MPU Clock/Reset/Power Mode Control */
-static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_clkm_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* ARM_CKCTL */
return s->clkm.arm_ckctl;
@@ -1614,7 +1623,7 @@ static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
}
static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint16_t diff;
@@ -1624,6 +1633,10 @@ static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
"mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
};
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* ARM_CKCTL */
diff = s->clkm.arm_ckctl ^ value;
@@ -1690,22 +1703,21 @@ static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_clkm_readfn[] = {
- omap_badwidth_read16,
- omap_clkm_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_clkm_writefn[] = {
- omap_badwidth_write16,
- omap_clkm_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_clkm_ops = {
+ .read = omap_clkm_read,
+ .write = omap_clkm_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (addr) {
case 0x04: /* DSP_IDLECT1 */
return s->clkm.dsp_idlect1;
@@ -1742,11 +1754,15 @@ static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
}
static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint16_t diff;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (addr) {
case 0x04: /* DSP_IDLECT1 */
diff = s->clkm.dsp_idlect1 ^ value;
@@ -1773,16 +1789,10 @@ static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_clkdsp_readfn[] = {
- omap_badwidth_read16,
- omap_clkdsp_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_clkdsp_writefn[] = {
- omap_badwidth_write16,
- omap_clkdsp_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_clkdsp_ops = {
+ .read = omap_clkdsp_read,
+ .write = omap_clkdsp_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_clkm_reset(struct omap_mpu_state_s *s)
@@ -1808,15 +1818,13 @@ static void omap_clkm_reset(struct omap_mpu_state_s *s)
s->clkm.dsp_rstct2 = 0x0000;
}
-static void omap_clkm_init(target_phys_addr_t mpu_base,
+static void omap_clkm_init(MemoryRegion *memory, target_phys_addr_t mpu_base,
target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
{
- int iomemtype[2] = {
- cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s,
- DEVICE_NATIVE_ENDIAN),
- cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s,
- DEVICE_NATIVE_ENDIAN),
- };
+ memory_region_init_io(&s->clkm_iomem, &omap_clkm_ops, s,
+ "omap-clkm", 0x100);
+ memory_region_init_io(&s->clkdsp_iomem, &omap_clkdsp_ops, s,
+ "omap-clkdsp", 0x1000);
s->clkm.arm_idlect1 = 0x03ff;
s->clkm.arm_idlect2 = 0x0100;
@@ -1824,8 +1832,8 @@ static void omap_clkm_init(target_phys_addr_t mpu_base,
omap_clkm_reset(s);
s->clkm.cold_start = 0x3a;
- cpu_register_physical_memory(mpu_base, 0x100, iomemtype[0]);
- cpu_register_physical_memory(dsp_base, 0x1000, iomemtype[1]);
+ memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem);
+ memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem);
}
/* MPU I/O */
@@ -1835,6 +1843,7 @@ struct omap_mpuio_s {
qemu_irq *in;
qemu_irq handler[16];
qemu_irq wakeup;
+ MemoryRegion iomem;
uint16_t inputs;
uint16_t outputs;
@@ -1889,12 +1898,17 @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
s->row_latch = ~rows;
}
-static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_mpuio_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (offset) {
case 0x00: /* INPUT_LATCH */
return s->inputs;
@@ -1945,13 +1959,17 @@ static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
}
static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t diff;
int ln;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (offset) {
case 0x04: /* OUTPUT_REG */
diff = (s->outputs ^ value) & ~s->dir;
@@ -2017,16 +2035,10 @@ static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const omap_mpuio_readfn[] = {
- omap_badwidth_read16,
- omap_mpuio_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_mpuio_writefn[] = {
- omap_badwidth_write16,
- omap_mpuio_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_mpuio_ops = {
+ .read = omap_mpuio_read,
+ .write = omap_mpuio_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_mpuio_reset(struct omap_mpuio_s *s)
@@ -2054,11 +2066,11 @@ static void omap_mpuio_onoff(void *opaque, int line, int on)
omap_mpuio_kbd_update(s);
}
-struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
+struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
+ target_phys_addr_t base,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk)
{
- int iomemtype;
struct omap_mpuio_s *s = (struct omap_mpuio_s *)
g_malloc0(sizeof(struct omap_mpuio_s));
@@ -2068,9 +2080,9 @@ struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
omap_mpuio_reset(s);
- iomemtype = cpu_register_io_memory(omap_mpuio_readfn,
- omap_mpuio_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x800, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_mpuio_ops, s,
+ "omap-mpuio", 0x800);
+ memory_region_add_subregion(memory, base, &s->iomem);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
@@ -3779,7 +3791,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
(imif_base = qemu_ram_alloc(NULL, "omap1.sram",
s->sram_size)) | IO_MEM_RAM);
- omap_clkm_init(0xfffece00, 0xe1008000, s);
+ omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
cpu_irq = arm_pic_init_cpu(s->env);
s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s->irq[0],
@@ -3843,7 +3855,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
s->irq[0][OMAP_INT_BRIDGE_PUB],
omap_findclk(s, "tipb_ck"));
- omap_tcmi_init(0xfffecc00, s);
+ omap_tcmi_init(system_memory, 0xfffecc00, s);
s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
omap_findclk(s, "uart1_ck"),
@@ -3864,9 +3876,12 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
"uart3",
serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
- omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
- omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
- omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
+ omap_dpll_init(system_memory,
+ &s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
+ omap_dpll_init(system_memory,
+ &s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
+ omap_dpll_init(system_memory,
+ &s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
dinfo = drive_get(IF_SD, 0, 0);
if (!dinfo) {
@@ -3877,7 +3892,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
omap_findclk(s, "mmc_ck"));
- s->mpuio = omap_mpuio_init(0xfffb5000,
+ s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000,
s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO],
s->wakeup, omap_findclk(s, "clk32-kHz"));
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 09/19] pci: add pci_address_space_io()
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
` (7 preceding siblings ...)
2011-08-25 8:09 ` [Qemu-devel] [PATCH 08/19] omap1: convert to memory API (part II) Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 10/19] isa: Pass i/o address space to isa_bus_new Avi Kivity
` (9 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <rth@twiddle.net>
Returns the I/O address space. Useful for implementing
PCI-ISA bridge devices.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/pci.c | 5 +++++
hw/pci.h | 1 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 6124790..1a5d2b6 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -2170,3 +2170,8 @@ MemoryRegion *pci_address_space(PCIDevice *dev)
{
return dev->bus->address_space_mem;
}
+
+MemoryRegion *pci_address_space_io(PCIDevice *dev)
+{
+ return dev->bus->address_space_io;
+}
diff --git a/hw/pci.h b/hw/pci.h
index 391217e..6bdbe4c 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -221,6 +221,7 @@ void pci_default_write_config(PCIDevice *d,
void pci_device_save(PCIDevice *s, QEMUFile *f);
int pci_device_load(PCIDevice *s, QEMUFile *f);
MemoryRegion *pci_address_space(PCIDevice *dev);
+MemoryRegion *pci_address_space_io(PCIDevice *dev);
typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 10/19] isa: Pass i/o address space to isa_bus_new
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
` (8 preceding siblings ...)
2011-08-25 8:09 ` [Qemu-devel] [PATCH 09/19] pci: add pci_address_space_io() Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 11/19] isa: add isa_register_ioport() Avi Kivity
` (8 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <rth@twiddle.net>
Not used yet, but at least we're provided with the correct region.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/isa-bus.c | 4 +++-
hw/isa.h | 2 +-
hw/mips_jazz.c | 17 ++++++++++-------
hw/mips_r4k.c | 2 +-
hw/pc_piix.c | 2 +-
hw/piix4.c | 2 +-
hw/piix_pci.c | 2 +-
hw/ppc_prep.c | 2 +-
hw/sun4u.c | 2 +-
hw/vt82c686.c | 2 +-
10 files changed, 21 insertions(+), 16 deletions(-)
diff --git a/hw/isa-bus.c b/hw/isa-bus.c
index 1cb497f..d067505 100644
--- a/hw/isa-bus.c
+++ b/hw/isa-bus.c
@@ -24,6 +24,7 @@
struct ISABus {
BusState qbus;
+ MemoryRegion *address_space_io;
qemu_irq *irqs;
};
static ISABus *isabus;
@@ -39,7 +40,7 @@ static struct BusInfo isa_bus_info = {
.get_fw_dev_path = isabus_get_fw_dev_path,
};
-ISABus *isa_bus_new(DeviceState *dev)
+ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space_io)
{
if (isabus) {
fprintf(stderr, "Can't create a second ISA bus\n");
@@ -51,6 +52,7 @@ ISABus *isa_bus_new(DeviceState *dev)
}
isabus = FROM_QBUS(ISABus, qbus_create(&isa_bus_info, dev, NULL));
+ isabus->address_space_io = address_space_io;
return isabus;
}
diff --git a/hw/isa.h b/hw/isa.h
index f344699..390e2d4 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -25,7 +25,7 @@ struct ISADeviceInfo {
isa_qdev_initfn init;
};
-ISABus *isa_bus_new(DeviceState *dev);
+ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space_io);
void isa_bus_irqs(qemu_irq *irqs);
qemu_irq isa_get_irq(int isairq);
void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq);
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 91e15b9..4aa5aa4 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -102,10 +102,11 @@ static void cpu_request_exit(void *opaque, int irq, int level)
}
}
-static
-void mips_jazz_init (MemoryRegion *address_space, ram_addr_t ram_size,
- const char *cpu_model,
- enum jazz_model_e jazz_model)
+static void mips_jazz_init(MemoryRegion *address_space,
+ MemoryRegion *address_space_io,
+ ram_addr_t ram_size,
+ const char *cpu_model,
+ enum jazz_model_e jazz_model)
{
char *filename;
int bios_size, n;
@@ -181,7 +182,7 @@ void mips_jazz_init (MemoryRegion *address_space, ram_addr_t ram_size,
/* ISA devices */
i8259 = i8259_init(env->irq[4]);
- isa_bus_new(NULL);
+ isa_bus_new(NULL, address_space_io);
isa_bus_irqs(i8259);
cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
DMA_init(0, cpu_exit_irq);
@@ -286,7 +287,8 @@ void mips_magnum_init (ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- mips_jazz_init(get_system_memory(), ram_size, cpu_model, JAZZ_MAGNUM);
+ mips_jazz_init(get_system_memory(), get_system_io(),
+ ram_size, cpu_model, JAZZ_MAGNUM);
}
static
@@ -295,7 +297,8 @@ void mips_pica61_init (ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- mips_jazz_init(get_system_memory(), ram_size, cpu_model, JAZZ_PICA61);
+ mips_jazz_init(get_system_memory(), get_system_io(),
+ ram_size, cpu_model, JAZZ_PICA61);
}
static QEMUMachine mips_magnum_machine = {
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index efa4b05..670acd4 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -259,7 +259,7 @@ void mips_r4k_init (ram_addr_t ram_size,
/* The PIC is attached to the MIPS CPU INT0 pin */
i8259 = i8259_init(env->irq[2]);
- isa_bus_new(NULL);
+ isa_bus_new(NULL, get_system_io());
isa_bus_irqs(i8259);
rtc_init(2000, NULL);
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 75d96d9..9a8f580 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -149,7 +149,7 @@ static void pc_init1(MemoryRegion *system_memory,
} else {
pci_bus = NULL;
i440fx_state = NULL;
- isa_bus_new(NULL);
+ isa_bus_new(NULL, system_io);
}
isa_bus_irqs(isa_irq);
diff --git a/hw/piix4.c b/hw/piix4.c
index 9590e7b..2fd1171 100644
--- a/hw/piix4.c
+++ b/hw/piix4.c
@@ -87,7 +87,7 @@ static int piix4_initfn(PCIDevice *dev)
{
PIIX4State *d = DO_UPCAST(PIIX4State, dev, dev);
- isa_bus_new(&d->dev.qdev);
+ isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
piix4_dev = &d->dev;
qemu_register_reset(piix4_reset, d);
return 0;
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 8f6ea42..d183443 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -504,7 +504,7 @@ static int piix3_initfn(PCIDevice *dev)
{
PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
- isa_bus_new(&d->dev.qdev);
+ isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
qemu_register_reset(piix3_reset, d);
return 0;
}
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 515de42..f9325bd 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -651,7 +651,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
pci_bus = pci_prep_init(i8259, get_system_memory(), get_system_io());
/* Hmm, prep has no pci-isa bridge ??? */
- isa_bus_new(NULL);
+ isa_bus_new(NULL, get_system_io());
isa_bus_irqs(i8259);
// pci_bus = i440fx_init();
/* Register 8 MB of ISA IO space (needed for non-contiguous map) */
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 1b60e4e..6b2983b 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -544,7 +544,7 @@ pci_ebus_init1(PCIDevice *pci_dev)
{
EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
- isa_bus_new(&pci_dev->qdev);
+ isa_bus_new(&pci_dev->qdev, pci_address_space_io(pci_dev));
pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
pci_dev->config[0x05] = 0x00;
diff --git a/hw/vt82c686.c b/hw/vt82c686.c
index 5c973ed..e2b179e 100644
--- a/hw/vt82c686.c
+++ b/hw/vt82c686.c
@@ -490,7 +490,7 @@ static int vt82c686b_initfn(PCIDevice *d)
uint8_t *wmask;
int i;
- isa_bus_new(&d->qdev);
+ isa_bus_new(&d->qdev, pci_address_space_io(d));
pci_conf = d->config;
pci_config_set_prog_interface(pci_conf, 0x0);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 11/19] isa: add isa_register_ioport()
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
` (9 preceding siblings ...)
2011-08-25 8:09 ` [Qemu-devel] [PATCH 10/19] isa: Pass i/o address space to isa_bus_new Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 12/19] pc: Re-order pc_init1 to initialize the ISA bus before ISA devices Avi Kivity
` (7 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <rth@twiddle.net>
To replace isa_init_ioport and isa_init_ioport_range
as the ISA devices are converted to the memory api.
[avi: use memory_region_size()]
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/isa-bus.c | 10 ++++++++++
hw/isa.h | 5 ++++-
2 files changed, 14 insertions(+), 1 deletions(-)
diff --git a/hw/isa-bus.c b/hw/isa-bus.c
index d067505..6c15a31 100644
--- a/hw/isa-bus.c
+++ b/hw/isa-bus.c
@@ -108,6 +108,16 @@ void isa_init_ioport(ISADevice *dev, uint16_t ioport)
isa_init_ioport_range(dev, ioport, 1);
}
+void isa_register_ioport(ISADevice *dev, MemoryRegion *io, uint16_t start)
+{
+ memory_region_add_subregion(isabus->address_space_io, start, io);
+ if (dev != NULL) {
+ assert(dev->nio < ARRAY_SIZE(dev->io));
+ dev->io[dev->nio++] = io;
+ isa_init_ioport_range(dev, start, memory_region_size(io));
+ }
+}
+
static int isa_qdev_init(DeviceState *qdev, DeviceInfo *base)
{
ISADevice *dev = DO_UPCAST(ISADevice, qdev, qdev);
diff --git a/hw/isa.h b/hw/isa.h
index 390e2d4..432d17a 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -13,10 +13,12 @@ typedef struct ISADeviceInfo ISADeviceInfo;
struct ISADevice {
DeviceState qdev;
+ MemoryRegion *io[32];
uint32_t isairq[2];
- int nirqs;
uint16_t ioports[32];
+ int nirqs;
int nioports;
+ int nio;
};
typedef int (*isa_qdev_initfn)(ISADevice *dev);
@@ -29,6 +31,7 @@ ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space_io);
void isa_bus_irqs(qemu_irq *irqs);
qemu_irq isa_get_irq(int isairq);
void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq);
+void isa_register_ioport(ISADevice *dev, MemoryRegion *io, uint16_t start);
void isa_init_ioport(ISADevice *dev, uint16_t ioport);
void isa_init_ioport_range(ISADevice *dev, uint16_t start, uint16_t length);
void isa_qdev_register(ISADeviceInfo *info);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 12/19] pc: Re-order pc_init1 to initialize the ISA bus before ISA devices
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
` (10 preceding siblings ...)
2011-08-25 8:09 ` [Qemu-devel] [PATCH 11/19] isa: add isa_register_ioport() Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 13/19] cs4231a: Convert to MemoryRegion Avi Kivity
` (6 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <rth@twiddle.net>
In particular, the i8259 was being initialized before the ISA bus,
leading to a crash.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/pc_piix.c | 22 ++++++++++++----------
1 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 9a8f580..322f267 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -123,17 +123,7 @@ static void pc_init1(MemoryRegion *system_memory,
pci_memory, &ram_memory);
}
- if (!xen_enabled()) {
- cpu_irq = pc_allocate_cpu_irq();
- i8259 = i8259_init(cpu_irq[0]);
- } else {
- i8259 = xen_interrupt_controller_init();
- }
isa_irq_state = g_malloc0(sizeof(*isa_irq_state));
- isa_irq_state->i8259 = i8259;
- if (pci_enabled) {
- ioapic_init(isa_irq_state);
- }
isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
if (pci_enabled) {
@@ -153,6 +143,18 @@ static void pc_init1(MemoryRegion *system_memory,
}
isa_bus_irqs(isa_irq);
+ if (!xen_enabled()) {
+ cpu_irq = pc_allocate_cpu_irq();
+ i8259 = i8259_init(cpu_irq[0]);
+ } else {
+ i8259 = xen_interrupt_controller_init();
+ }
+
+ isa_irq_state->i8259 = i8259;
+ if (pci_enabled) {
+ ioapic_init(isa_irq_state);
+ }
+
pc_register_ferr_irq(isa_get_irq(13));
pc_vga_init(pci_enabled? pci_bus: NULL);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 13/19] cs4231a: Convert to MemoryRegion
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
` (11 preceding siblings ...)
2011-08-25 8:09 ` [Qemu-devel] [PATCH 12/19] pc: Re-order pc_init1 to initialize the ISA bus before ISA devices Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 14/19] i8254: " Avi Kivity
` (5 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <rth@twiddle.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/cs4231a.c | 38 +++++++++++++++++++-------------------
1 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/hw/cs4231a.c b/hw/cs4231a.c
index 598f032..e16665e 100644
--- a/hw/cs4231a.c
+++ b/hw/cs4231a.c
@@ -59,6 +59,7 @@ static struct {
typedef struct CSState {
ISADevice dev;
QEMUSoundCard card;
+ MemoryRegion ioports;
qemu_irq pic;
uint32_t regs[CS_REGS];
uint8_t dregs[CS_DREGS];
@@ -74,14 +75,6 @@ typedef struct CSState {
int16_t *tab;
} CSState;
-#define IO_READ_PROTO(name) \
- static uint32_t name (void *opaque, uint32_t addr)
-
-#define IO_WRITE_PROTO(name) \
- static void name (void *opaque, uint32_t addr, uint32_t val)
-
-#define GET_SADDR(addr) (addr & 3)
-
#define MODE2 (1 << 6)
#define MCE (1 << 6)
#define PMCE (1 << 4)
@@ -353,12 +346,12 @@ static void cs_reset_voices (CSState *s, uint32_t val)
}
}
-IO_READ_PROTO (cs_read)
+static uint64_t cs_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
CSState *s = opaque;
uint32_t saddr, iaddr, ret;
- saddr = GET_SADDR (addr);
+ saddr = addr;
iaddr = ~0U;
switch (saddr) {
@@ -390,12 +383,14 @@ IO_READ_PROTO (cs_read)
return ret;
}
-IO_WRITE_PROTO (cs_write)
+static void cs_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val64, unsigned size)
{
CSState *s = opaque;
- uint32_t saddr, iaddr;
+ uint32_t saddr, iaddr, val;
- saddr = GET_SADDR (addr);
+ saddr = addr;
+ val = val64;
switch (saddr) {
case Index_Address:
@@ -637,18 +632,23 @@ static const VMStateDescription vmstate_cs4231a = {
}
};
+static const MemoryRegionOps cs_ioport_ops = {
+ .read = cs_read,
+ .write = cs_write,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ }
+};
+
static int cs4231a_initfn (ISADevice *dev)
{
CSState *s = DO_UPCAST (CSState, dev, dev);
- int i;
isa_init_irq (dev, &s->pic, s->irq);
- for (i = 0; i < 4; i++) {
- isa_init_ioport(dev, i);
- register_ioport_write (s->port + i, 1, 1, cs_write, s);
- register_ioport_read (s->port + i, 1, 1, cs_read, s);
- }
+ memory_region_init_io(&s->ioports, &cs_ioport_ops, s, "cs4231a", 4);
+ isa_register_ioport(dev, &s->ioports, s->port);
DMA_register_channel (s->dma, cs_dma_read, s);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 14/19] i8254: Convert to MemoryRegion
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
` (12 preceding siblings ...)
2011-08-25 8:09 ` [Qemu-devel] [PATCH 13/19] cs4231a: Convert to MemoryRegion Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 15/19] i8259: " Avi Kivity
` (4 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <rth@twiddle.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/i8254.c | 16 +++++++++++++---
1 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/hw/i8254.c b/hw/i8254.c
index a9ca9f6..12571ef 100644
--- a/hw/i8254.c
+++ b/hw/i8254.c
@@ -55,6 +55,7 @@ typedef struct PITChannelState {
typedef struct PITState {
ISADevice dev;
+ MemoryRegion ioports;
uint32_t irq;
uint32_t iobase;
PITChannelState channels[3];
@@ -506,6 +507,16 @@ void hpet_pit_enable(void)
pit_load_count(s, 0);
}
+static const MemoryRegionPortio pit_portio[] = {
+ { 0, 4, 1, .write = pit_ioport_write },
+ { 0, 3, 1, .read = pit_ioport_read },
+ PORTIO_END_OF_LIST()
+};
+
+static const MemoryRegionOps pit_ioport_ops = {
+ .old_portio = pit_portio
+};
+
static int pit_initfn(ISADevice *dev)
{
PITState *pit = DO_UPCAST(PITState, dev, dev);
@@ -516,9 +527,8 @@ static int pit_initfn(ISADevice *dev)
s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
s->irq = isa_get_irq(pit->irq);
- register_ioport_write(pit->iobase, 4, 1, pit_ioport_write, pit);
- register_ioport_read(pit->iobase, 3, 1, pit_ioport_read, pit);
- isa_init_ioport(dev, pit->iobase);
+ memory_region_init_io(&pit->ioports, &pit_ioport_ops, pit, "pit", 4);
+ isa_register_ioport(dev, &pit->ioports, pit->iobase);
qdev_set_legacy_instance_id(&dev->qdev, pit->iobase, 2);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 15/19] i8259: Convert to MemoryRegion
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
` (13 preceding siblings ...)
2011-08-25 8:09 ` [Qemu-devel] [PATCH 14/19] i8254: " Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 16/19] pckbd: " Avi Kivity
` (3 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <rth@twiddle.net>
The only non-obvious part is pic_poll_read which used
"addr1 >> 7" to detect whether one referred to either
the master or slave PIC. Instead, test this directly.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/i8259.c | 65 ++++++++++++++++++++++++++++++++++++++++++-----------------
1 files changed, 46 insertions(+), 19 deletions(-)
diff --git a/hw/i8259.c b/hw/i8259.c
index c0b96ab..e5323ff 100644
--- a/hw/i8259.c
+++ b/hw/i8259.c
@@ -59,6 +59,8 @@ typedef struct PicState {
uint8_t elcr; /* PIIX edge/trigger selection*/
uint8_t elcr_mask;
PicState2 *pics_state;
+ MemoryRegion base_io;
+ MemoryRegion elcr_io;
} PicState;
struct PicState2 {
@@ -284,13 +286,15 @@ static void pic_reset(void *opaque)
/* Note: ELCR is not reset */
}
-static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
+static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
+ uint64_t val64, unsigned size)
{
PicState *s = opaque;
+ uint32_t addr = addr64;
+ uint32_t val = val64;
int priority, cmd, irq;
DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val);
- addr &= 1;
if (addr == 0) {
if (val & 0x10) {
/* init */
@@ -374,19 +378,21 @@ static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
}
}
-static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
+static uint32_t pic_poll_read(PicState *s)
{
int ret;
ret = pic_get_irq(s);
if (ret >= 0) {
- if (addr1 >> 7) {
+ bool slave = (s == &isa_pic->pics[1]);
+
+ if (slave) {
s->pics_state->pics[0].isr &= ~(1 << 2);
s->pics_state->pics[0].irr &= ~(1 << 2);
}
s->irr &= ~(1 << ret);
s->isr &= ~(1 << ret);
- if (addr1 >> 7 || ret != 2)
+ if (slave || ret != 2)
pic_update_irq(s->pics_state);
} else {
ret = 0x07;
@@ -396,16 +402,15 @@ static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
return ret;
}
-static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
+static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr1,
+ unsigned size)
{
PicState *s = opaque;
- unsigned int addr;
+ unsigned int addr = addr1;
int ret;
- addr = addr1;
- addr &= 1;
if (s->poll) {
- ret = pic_poll_read(s, addr1);
+ ret = pic_poll_read(s);
s->poll = 0;
} else {
if (addr == 0) {
@@ -417,7 +422,7 @@ static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
ret = s->imr;
}
}
- DPRINTF("read: addr=0x%02x val=0x%02x\n", addr1, ret);
+ DPRINTF("read: addr=0x%02x val=0x%02x\n", addr, ret);
return ret;
}
@@ -427,22 +432,24 @@ uint32_t pic_intack_read(PicState2 *s)
{
int ret;
- ret = pic_poll_read(&s->pics[0], 0x00);
+ ret = pic_poll_read(&s->pics[0]);
if (ret == 2)
- ret = pic_poll_read(&s->pics[1], 0x80) + 8;
+ ret = pic_poll_read(&s->pics[1]) + 8;
/* Prepare for ISR read */
s->pics[0].read_reg_select = 1;
return ret;
}
-static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
+static void elcr_ioport_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
PicState *s = opaque;
s->elcr = val & s->elcr_mask;
}
-static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
+static uint64_t elcr_ioport_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
PicState *s = opaque;
return s->elcr;
@@ -474,15 +481,35 @@ static const VMStateDescription vmstate_pic = {
}
};
+static const MemoryRegionOps pic_base_ioport_ops = {
+ .read = pic_ioport_read,
+ .write = pic_ioport_write,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
+static const MemoryRegionOps pic_elcr_ioport_ops = {
+ .read = elcr_ioport_read,
+ .write = elcr_ioport_write,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
/* XXX: add generic master/slave system */
static void pic_init1(int io_addr, int elcr_addr, PicState *s)
{
- register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
- register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
+ memory_region_init_io(&s->base_io, &pic_base_ioport_ops, s, "pic", 2);
+ memory_region_init_io(&s->elcr_io, &pic_elcr_ioport_ops, s, "elcr", 1);
+
+ isa_register_ioport(NULL, &s->base_io, io_addr);
if (elcr_addr >= 0) {
- register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
- register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
+ isa_register_ioport(NULL, &s->elcr_io, elcr_addr);
}
+
vmstate_register(NULL, io_addr, &vmstate_pic, s);
qemu_register_reset(pic_reset, s);
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 16/19] pckbd: Convert to MemoryRegion
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
` (14 preceding siblings ...)
2011-08-25 8:09 ` [Qemu-devel] [PATCH 15/19] i8259: " Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 17/19] serial: Convert serial_isa_initfn " Avi Kivity
` (2 subsequent siblings)
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <rth@twiddle.net>
Slightly non-obvious with mips_jazz passing in the region
structure to populate.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/mips_jazz.c | 4 ++-
hw/pc.h | 2 +-
hw/pckbd.c | 59 ++++++++++++++++++++++++++++++++++---------------------
3 files changed, 40 insertions(+), 25 deletions(-)
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 4aa5aa4..8a3c3b0 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -115,6 +115,7 @@ static void mips_jazz_init(MemoryRegion *address_space,
rc4030_dma *dmas;
void* rc4030_opaque;
MemoryRegion *rtc = g_new(MemoryRegion, 1);
+ MemoryRegion *i8042 = g_new(MemoryRegion, 1);
MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
NICInfo *nd;
DeviceState *dev;
@@ -245,7 +246,8 @@ static void mips_jazz_init(MemoryRegion *address_space,
memory_region_add_subregion(address_space, 0x80004000, rtc);
/* Keyboard (i8042) */
- i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
+ i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1);
+ memory_region_add_subregion(address_space, 0x80005000, i8042);
/* Serial ports */
if (serial_hds[0]) {
diff --git a/hw/pc.h b/hw/pc.h
index dae736e..28ed210 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -118,7 +118,7 @@ void vmmouse_set_data(const uint32_t *data);
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
- target_phys_addr_t base, ram_addr_t size,
+ MemoryRegion *region, ram_addr_t size,
target_phys_addr_t mask);
void i8042_isa_mouse_fake_event(void *opaque);
void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
diff --git a/hw/pckbd.c b/hw/pckbd.c
index a272ccd..06b40c5 100644
--- a/hw/pckbd.c
+++ b/hw/pckbd.c
@@ -400,33 +400,27 @@ static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value
kbd_write_data(s, 0, value & 0xff);
}
-static CPUReadMemoryFunc * const kbd_mm_read[] = {
- &kbd_mm_readb,
- &kbd_mm_readb,
- &kbd_mm_readb,
-};
-
-static CPUWriteMemoryFunc * const kbd_mm_write[] = {
- &kbd_mm_writeb,
- &kbd_mm_writeb,
- &kbd_mm_writeb,
+static const MemoryRegionOps i8042_mmio_ops = {
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .old_mmio = {
+ .read = { kbd_mm_readb, kbd_mm_readb, kbd_mm_readb },
+ .write = { kbd_mm_writeb, kbd_mm_writeb, kbd_mm_writeb },
+ },
};
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
- target_phys_addr_t base, ram_addr_t size,
+ MemoryRegion *region, ram_addr_t size,
target_phys_addr_t mask)
{
KBDState *s = g_malloc0(sizeof(KBDState));
- int s_io_memory;
s->irq_kbd = kbd_irq;
s->irq_mouse = mouse_irq;
s->mask = mask;
vmstate_register(NULL, 0, &vmstate_kbd, s);
- s_io_memory = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, size, s_io_memory);
+
+ memory_region_init_io(region, &i8042_mmio_ops, s, "i8042", size);
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
@@ -435,7 +429,8 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
typedef struct ISAKBDState {
ISADevice dev;
- KBDState kbd;
+ KBDState kbd;
+ MemoryRegion io[2];
} ISAKBDState;
void i8042_isa_mouse_fake_event(void *opaque)
@@ -464,19 +459,37 @@ static const VMStateDescription vmstate_kbd_isa = {
}
};
+static const MemoryRegionPortio i8042_data_portio[] = {
+ { 0, 1, 1, .read = kbd_read_data, .write = kbd_write_data },
+ PORTIO_END_OF_LIST()
+};
+
+static const MemoryRegionPortio i8042_cmd_portio[] = {
+ { 0, 1, 1, .read = kbd_read_status, .write = kbd_write_command },
+ PORTIO_END_OF_LIST()
+};
+
+static const MemoryRegionOps i8042_data_ops = {
+ .old_portio = i8042_data_portio
+};
+
+static const MemoryRegionOps i8042_cmd_ops = {
+ .old_portio = i8042_cmd_portio
+};
+
static int i8042_initfn(ISADevice *dev)
{
- KBDState *s = &(DO_UPCAST(ISAKBDState, dev, dev)->kbd);
+ ISAKBDState *isa_s = DO_UPCAST(ISAKBDState, dev, dev);
+ KBDState *s = &isa_s->kbd;
isa_init_irq(dev, &s->irq_kbd, 1);
isa_init_irq(dev, &s->irq_mouse, 12);
- register_ioport_read(0x60, 1, 1, kbd_read_data, s);
- register_ioport_write(0x60, 1, 1, kbd_write_data, s);
- isa_init_ioport(dev, 0x60);
- register_ioport_read(0x64, 1, 1, kbd_read_status, s);
- register_ioport_write(0x64, 1, 1, kbd_write_command, s);
- isa_init_ioport(dev, 0x64);
+ memory_region_init_io(isa_s->io + 0, &i8042_data_ops, s, "i8042-data", 1);
+ isa_register_ioport(dev, isa_s->io + 0, 0x60);
+
+ memory_region_init_io(isa_s->io + 1, &i8042_cmd_ops, s, "i8042-cmd", 1);
+ isa_register_ioport(dev, isa_s->io + 1, 0x64);
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 17/19] serial: Convert serial_isa_initfn to MemoryRegion
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
` (15 preceding siblings ...)
2011-08-25 8:09 ` [Qemu-devel] [PATCH 16/19] pckbd: " Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 18/19] fdc: Convert isabus_fdc_init1 " Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 19/19] pci: simplify memory region registration Avi Kivity
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <rth@twiddle.net>
The serial_mm_init path is as yet unconverted.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/serial.c | 15 ++++++++++++---
1 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/hw/serial.c b/hw/serial.c
index ed7fd0a..2e6d212 100644
--- a/hw/serial.c
+++ b/hw/serial.c
@@ -157,6 +157,7 @@ struct SerialState {
typedef struct ISASerialState {
ISADevice dev;
+ MemoryRegion io;
uint32_t index;
uint32_t iobase;
uint32_t isairq;
@@ -755,6 +756,15 @@ void serial_set_frequency(SerialState *s, uint32_t frequency)
static const int isa_serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
static const int isa_serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
+static const MemoryRegionPortio serial_portio[] = {
+ { 0, 8, 1, .read = serial_ioport_read, .write = serial_ioport_write },
+ PORTIO_END_OF_LIST()
+};
+
+static const MemoryRegionOps serial_io_ops = {
+ .old_portio = serial_portio
+};
+
static int serial_isa_initfn(ISADevice *dev)
{
static int index;
@@ -776,9 +786,8 @@ static int serial_isa_initfn(ISADevice *dev)
serial_init_core(s);
qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 3);
- register_ioport_write(isa->iobase, 8, 1, serial_ioport_write, s);
- register_ioport_read(isa->iobase, 8, 1, serial_ioport_read, s);
- isa_init_ioport_range(dev, isa->iobase, 8);
+ memory_region_init_io(&isa->io, &serial_io_ops, s, "serial", 8);
+ isa_register_ioport(dev, &isa->io, isa->iobase);
return 0;
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 18/19] fdc: Convert isabus_fdc_init1 to MemoryRegion
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
` (16 preceding siblings ...)
2011-08-25 8:09 ` [Qemu-devel] [PATCH 17/19] serial: Convert serial_isa_initfn " Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
2011-08-25 8:09 ` [Qemu-devel] [PATCH 19/19] pci: simplify memory region registration Avi Kivity
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <rth@twiddle.net>
This requires some amount of hoop-jumping, so that we don't
inadvertently claim port 0x3f6, which is used by ISA IDE.
The sysbus initialization path is as yet unconverted.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/fdc.c | 53 +++++++++++++++++++++++++++++++++--------------------
1 files changed, 33 insertions(+), 20 deletions(-)
diff --git a/hw/fdc.c b/hw/fdc.c
index 580b657..c3ae956 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -425,6 +425,7 @@ typedef struct FDCtrlSysBus {
typedef struct FDCtrlISABus {
ISADevice busdev;
+ MemoryRegion io_0, io_7;
struct FDCtrl state;
int32_t bootindexA;
int32_t bootindexB;
@@ -490,16 +491,6 @@ static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
}
}
-static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
-{
- return fdctrl_read(opaque, reg & 7);
-}
-
-static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
-{
- fdctrl_write(opaque, reg & 7, value);
-}
-
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
{
return fdctrl_read(opaque, (uint32_t)reg);
@@ -1891,6 +1882,34 @@ static int fdctrl_init_common(FDCtrl *fdctrl)
return fdctrl_connect_drives(fdctrl);
}
+static uint32_t fdctrl_read_port_7(void *opaque, uint32_t reg)
+{
+ return fdctrl_read(opaque, reg + 7);
+}
+
+static void fdctrl_write_port_7(void *opaque, uint32_t reg, uint32_t value)
+{
+ fdctrl_write(opaque, reg + 7, value);
+}
+
+static const MemoryRegionPortio fdc_portio_0[] = {
+ { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
+ PORTIO_END_OF_LIST()
+};
+
+static const MemoryRegionPortio fdc_portio_7[] = {
+ { 0, 1, 1, .read = fdctrl_read_port_7, .write = fdctrl_write_port_7 },
+ PORTIO_END_OF_LIST()
+};
+
+static const MemoryRegionOps fdc_ioport_0_ops = {
+ .old_portio = fdc_portio_0
+};
+
+static const MemoryRegionOps fdc_ioport_7_ops = {
+ .old_portio = fdc_portio_7
+};
+
static int isabus_fdc_init1(ISADevice *dev)
{
FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
@@ -1900,16 +1919,10 @@ static int isabus_fdc_init1(ISADevice *dev)
int dma_chann = 2;
int ret;
- register_ioport_read(iobase + 0x01, 5, 1,
- &fdctrl_read_port, fdctrl);
- register_ioport_read(iobase + 0x07, 1, 1,
- &fdctrl_read_port, fdctrl);
- register_ioport_write(iobase + 0x01, 5, 1,
- &fdctrl_write_port, fdctrl);
- register_ioport_write(iobase + 0x07, 1, 1,
- &fdctrl_write_port, fdctrl);
- isa_init_ioport_range(dev, iobase, 6);
- isa_init_ioport(dev, iobase + 7);
+ memory_region_init_io(&isa->io_0, &fdc_ioport_0_ops, fdctrl, "fdc", 6);
+ memory_region_init_io(&isa->io_7, &fdc_ioport_7_ops, fdctrl, "fdc", 1);
+ isa_register_ioport(dev, &isa->io_0, iobase);
+ isa_register_ioport(dev, &isa->io_7, iobase + 7);
isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
fdctrl->dma_chann = dma_chann;
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 19/19] pci: simplify memory region registration
2011-08-25 8:08 [Qemu-devel] [PATCH 00/19] Memory API conversions: batch 6 Avi Kivity
` (17 preceding siblings ...)
2011-08-25 8:09 ` [Qemu-devel] [PATCH 18/19] fdc: Convert isabus_fdc_init1 " Avi Kivity
@ 2011-08-25 8:09 ` Avi Kivity
18 siblings, 0 replies; 20+ messages in thread
From: Avi Kivity @ 2011-08-25 8:09 UTC (permalink / raw)
To: qemu-devel
The two code paths (for ADDRESS_SPACE_IO and ADDRESS_SPACE_MEM) are almost
identical. Unify them.
Signed-off-by: Avi Kivity <avi@redhat.com>
---
hw/pci.c | 15 ++++-----------
1 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 1a5d2b6..e9e37ef 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1059,18 +1059,11 @@ static void pci_update_mappings(PCIDevice *d)
* Teach them such cases, such that filtered_size < size and
* addr & (size - 1) != 0.
*/
- if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
- memory_region_add_subregion_overlap(r->address_space,
- r->addr,
- r->memory,
- 1);
- } else {
- memory_region_add_subregion_overlap(r->address_space,
- pci_to_cpu_addr(d->bus,
- r->addr),
- r->memory,
- 1);
+ if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO)) {
+ new_addr = pci_to_cpu_addr(d->bus, new_addr);
}
+ memory_region_add_subregion_overlap(r->address_space,
+ new_addr, r->memory, 1);
}
}
}
--
1.7.5.3
^ permalink raw reply related [flat|nested] 20+ messages in thread