* [Qemu-devel] [PATCH 1/6] target-alpha: Add custom PALcode image for CLIPPER emulation.
2011-08-25 21:45 [Qemu-devel] [PULL][PATCH 0/6] Alpha system emulation, v9 Richard Henderson
@ 2011-08-25 21:45 ` Richard Henderson
2011-08-26 4:09 ` Peter Maydell
2011-08-25 21:45 ` [Qemu-devel] [PATCH 2/6] target-alpha: Add " Richard Henderson
` (5 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Richard Henderson @ 2011-08-25 21:45 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
.gitmodules | 3 +++
Makefile | 3 ++-
configure | 8 +++++++-
pc-bios/README | 3 +++
pc-bios/palcode-clipper | Bin 0 -> 185703 bytes
roms/qemu-palcode | 1 +
6 files changed, 16 insertions(+), 2 deletions(-)
create mode 100755 pc-bios/palcode-clipper
create mode 160000 roms/qemu-palcode
diff --git a/.gitmodules b/.gitmodules
index 7884471..528743d 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -10,3 +10,6 @@
[submodule "roms/ipxe"]
path = roms/ipxe
url = git://git.qemu.org/ipxe.git
+[submodule "roms/qemu-palcode"]
+ path = roms/qemu-palcode
+ url = git://repo.or.cz/qemu-palcode.git
diff --git a/Makefile b/Makefile
index 8606849..578d853 100644
--- a/Makefile
+++ b/Makefile
@@ -247,7 +247,8 @@ bamboo.dtb petalogix-s3adsp1800.dtb petalogix-ml605.dtb \
mpc8544ds.dtb \
multiboot.bin linuxboot.bin \
s390-zipl.rom \
-spapr-rtas.bin slof.bin
+spapr-rtas.bin slof.bin \
+palcode-sx164
else
BLOBS=
endif
diff --git a/configure b/configure
index 1340c33..d826a48 100755
--- a/configure
+++ b/configure
@@ -3606,7 +3606,13 @@ FILES="$FILES tests/cris/Makefile tests/cris/.gdbinit"
FILES="$FILES pc-bios/optionrom/Makefile pc-bios/keymaps"
FILES="$FILES pc-bios/spapr-rtas/Makefile"
FILES="$FILES roms/seabios/Makefile roms/vgabios/Makefile"
-for bios_file in $source_path/pc-bios/*.bin $source_path/pc-bios/*.rom $source_path/pc-bios/*.dtb $source_path/pc-bios/openbios-*; do
+for bios_file in \
+ $source_path/pc-bios/*.bin \
+ $source_path/pc-bios/*.rom \
+ $source_path/pc-bios/*.dtb \
+ $source_path/pc-bios/openbios-* \
+ $source_path/pc-bios/palcode-*
+do
FILES="$FILES pc-bios/`basename $bios_file`"
done
mkdir -p $DIRS
diff --git a/pc-bios/README b/pc-bios/README
index f74b246..861227a 100644
--- a/pc-bios/README
+++ b/pc-bios/README
@@ -32,3 +32,6 @@
- The S390 zipl loader is an addition to the official IBM s390-tools
package. That fork is maintained in its own git repository at:
git://repo.or.cz/s390-tools.git
+
+- The Alpha palcode image is available from:
+ git://repo.or.cz/qemu-palcode.git
diff --git a/pc-bios/palcode-clipper b/pc-bios/palcode-clipper
new file mode 100755
index 0000000000000000000000000000000000000000..a92372c107af72071e265e1ca94b9ae5573bd317
GIT binary patch
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diff --git a/roms/qemu-palcode b/roms/qemu-palcode
new file mode 160000
index 0000000..7abb12f
--- /dev/null
+++ b/roms/qemu-palcode
@@ -0,0 +1 @@
+Subproject commit 7abb12f60eb3069019e9497e193733d77d8f0722
--
1.7.4.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH 1/6] target-alpha: Add custom PALcode image for CLIPPER emulation.
2011-08-25 21:45 ` [Qemu-devel] [PATCH 1/6] target-alpha: Add custom PALcode image for CLIPPER emulation Richard Henderson
@ 2011-08-26 4:09 ` Peter Maydell
0 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2011-08-26 4:09 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
2011/8/25 Richard Henderson <rth@twiddle.net>:
> diff --git a/.gitmodules b/.gitmodules
> index 7884471..528743d 100644
> --- a/.gitmodules
> +++ b/.gitmodules
> @@ -10,3 +10,6 @@
> [submodule "roms/ipxe"]
> path = roms/ipxe
> url = git://git.qemu.org/ipxe.git
> +[submodule "roms/qemu-palcode"]
> + path = roms/qemu-palcode
> + url = git://repo.or.cz/qemu-palcode.git
We had a conversation on IRC about binary blobs the other day,
and I think Anthony said that all submodules referred to here
had to also be on git.qemu.org. But I could be misremembering.
(In particular I thought Anthony said these were all relative
references, which they clearly aren't...)
> diff --git a/Makefile b/Makefile
> index 8606849..578d853 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -247,7 +247,8 @@ bamboo.dtb petalogix-s3adsp1800.dtb petalogix-ml605.dtb \
> mpc8544ds.dtb \
> multiboot.bin linuxboot.bin \
> s390-zipl.rom \
> -spapr-rtas.bin slof.bin
> +spapr-rtas.bin slof.bin \
> +palcode-sx164
> else
> BLOBS=
> endif
You don't update the list of blobs in the 'tarbin' target,
but I have a feeling that may be broken anyway. Does anybody
use it, and if not should we just nuke it?
> diff --git a/pc-bios/README b/pc-bios/README
> index f74b246..861227a 100644
> --- a/pc-bios/README
> +++ b/pc-bios/README
> @@ -32,3 +32,6 @@
> - The S390 zipl loader is an addition to the official IBM s390-tools
> package. That fork is maintained in its own git repository at:
> git://repo.or.cz/s390-tools.git
> +
> +- The Alpha palcode image is available from:
> + git://repo.or.cz/qemu-palcode.git
You mean "The Alpha palcode image sources"; the image will already
be in git :-)
-- PMM
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 2/6] target-alpha: Add CLIPPER emulation.
2011-08-25 21:45 [Qemu-devel] [PULL][PATCH 0/6] Alpha system emulation, v9 Richard Henderson
2011-08-25 21:45 ` [Qemu-devel] [PATCH 1/6] target-alpha: Add custom PALcode image for CLIPPER emulation Richard Henderson
@ 2011-08-25 21:45 ` Richard Henderson
2011-08-25 21:45 ` [Qemu-devel] [PATCH 3/6] " Richard Henderson
` (4 subsequent siblings)
6 siblings, 0 replies; 17+ messages in thread
From: Richard Henderson @ 2011-08-25 21:45 UTC (permalink / raw)
To: qemu-devel
This is a DP264 variant, SMP capable, no unusual hardware present.
The emulation does not currently include any PCI IOMMU code.
Hopefully the generic support for that can be merged to HEAD soon.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
hw/alpha_typhoon.c | 794 ++++++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 794 insertions(+), 0 deletions(-)
create mode 100644 hw/alpha_typhoon.c
diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c
new file mode 100644
index 0000000..3637efc
--- /dev/null
+++ b/hw/alpha_typhoon.c
@@ -0,0 +1,794 @@
+/*
+ * DEC 21272 (TSUNAMI/TYPHOON) chipset emulation.
+ *
+ * Written by Richard Henderson.
+ *
+ * This work is licensed under the GNU GPL license version 2 or later.
+ */
+
+#include "cpu.h"
+#include "exec-all.h"
+#include "hw.h"
+#include "devices.h"
+#include "sysemu.h"
+#include "alpha_sys.h"
+#include "exec-memory.h"
+
+
+typedef struct TyphoonCchip {
+ MemoryRegion region;
+ uint64_t misc;
+ uint64_t drir;
+ uint64_t dim[4];
+ uint32_t iic[4];
+ CPUState *cpu[4];
+} TyphoonCchip;
+
+typedef struct TyphoonWindow {
+ uint32_t base_addr;
+ uint32_t mask;
+ uint32_t translated_base_pfn;
+} TyphoonWindow;
+
+typedef struct TyphoonPchip {
+ MemoryRegion region;
+ MemoryRegion reg_iack;
+ MemoryRegion reg_mem;
+ MemoryRegion reg_io;
+ MemoryRegion reg_conf;
+ uint64_t ctl;
+ TyphoonWindow win[4];
+} TyphoonPchip;
+
+typedef struct TyphoonState {
+ PCIHostState host;
+ TyphoonCchip cchip;
+ TyphoonPchip pchip;
+ MemoryRegion dchip_region;
+ MemoryRegion ram_region;
+
+ /* QEMU emulation state. */
+ uint32_t latch_tmp;
+} TyphoonState;
+
+/* Called when one of DRIR or DIM changes. */
+static void cpu_irq_change(CPUState *env, uint64_t req)
+{
+ /* If there are any non-masked interrupts, tell the cpu. */
+ if (env) {
+ if (req) {
+ cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ }
+ }
+}
+
+static uint64_t cchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
+{
+ CPUState *env = cpu_single_env;
+ TyphoonState *s = opaque;
+ uint64_t ret = 0;
+
+ if (addr & 4) {
+ return s->latch_tmp;
+ }
+
+ switch (addr) {
+ case 0x0000:
+ /* CSC: Cchip System Configuration Register. */
+ /* All sorts of data here; probably the only thing relevant is
+ PIP<14> Pchip 1 Present = 0. */
+ break;
+
+ case 0x0040:
+ /* MTR: Memory Timing Register. */
+ /* All sorts of stuff related to real DRAM. */
+ break;
+
+ case 0x0080:
+ /* MISC: Miscellaneous Register. */
+ ret = s->cchip.misc | (env->cpu_index & 3);
+ break;
+
+ case 0x00c0:
+ /* MPD: Memory Presence Detect Register. */
+ break;
+
+ case 0x0100: /* AAR0 */
+ case 0x0140: /* AAR1 */
+ case 0x0180: /* AAR2 */
+ case 0x01c0: /* AAR3 */
+ /* AAR: Array Address Register. */
+ /* All sorts of information about DRAM. */
+ break;
+
+ case 0x0200:
+ /* DIM0: Device Interrupt Mask Register, CPU0. */
+ ret = s->cchip.dim[0];
+ break;
+ case 0x0240:
+ /* DIM1: Device Interrupt Mask Register, CPU1. */
+ ret = s->cchip.dim[1];
+ break;
+ case 0x0280:
+ /* DIR0: Device Interrupt Request Register, CPU0. */
+ ret = s->cchip.dim[0] & s->cchip.drir;
+ break;
+ case 0x02c0:
+ /* DIR1: Device Interrupt Request Register, CPU1. */
+ ret = s->cchip.dim[1] & s->cchip.drir;
+ break;
+ case 0x0300:
+ /* DRIR: Device Raw Interrupt Request Register. */
+ ret = s->cchip.drir;
+ break;
+
+ case 0x0340:
+ /* PRBEN: Probe Enable Register. */
+ break;
+
+ case 0x0380:
+ /* IIC0: Interval Ignore Count Register, CPU0. */
+ ret = s->cchip.iic[0];
+ break;
+ case 0x03c0:
+ /* IIC1: Interval Ignore Count Register, CPU1. */
+ ret = s->cchip.iic[1];
+ break;
+
+ case 0x0400: /* MPR0 */
+ case 0x0440: /* MPR1 */
+ case 0x0480: /* MPR2 */
+ case 0x04c0: /* MPR3 */
+ /* MPR: Memory Programming Register. */
+ break;
+
+ case 0x0580:
+ /* TTR: TIGbus Timing Register. */
+ /* All sorts of stuff related to interrupt delivery timings. */
+ break;
+ case 0x05c0:
+ /* TDR: TIGbug Device Timing Register. */
+ break;
+
+ case 0x0600:
+ /* DIM2: Device Interrupt Mask Register, CPU2. */
+ ret = s->cchip.dim[2];
+ break;
+ case 0x0640:
+ /* DIM3: Device Interrupt Mask Register, CPU3. */
+ ret = s->cchip.dim[3];
+ break;
+ case 0x0680:
+ /* DIR2: Device Interrupt Request Register, CPU2. */
+ ret = s->cchip.dim[2] & s->cchip.drir;
+ break;
+ case 0x06c0:
+ /* DIR3: Device Interrupt Request Register, CPU3. */
+ ret = s->cchip.dim[3] & s->cchip.drir;
+ break;
+
+ case 0x0700:
+ /* IIC2: Interval Ignore Count Register, CPU2. */
+ ret = s->cchip.iic[2];
+ break;
+ case 0x0740:
+ /* IIC3: Interval Ignore Count Register, CPU3. */
+ ret = s->cchip.iic[3];
+ break;
+
+ case 0x0780:
+ /* PWR: Power Management Control. */
+ break;
+
+ case 0x0c00: /* CMONCTLA */
+ case 0x0c40: /* CMONCTLB */
+ case 0x0c80: /* CMONCNT01 */
+ case 0x0cc0: /* CMONCNT23 */
+ break;
+
+ default:
+ cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);
+ return -1;
+ }
+
+ s->latch_tmp = ret >> 32;
+ return ret;
+}
+
+static uint64_t dchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
+{
+ /* Skip this. It's all related to DRAM timing and setup. */
+ return 0;
+}
+
+static uint64_t pchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
+{
+ TyphoonState *s = opaque;
+ uint64_t ret = 0;
+
+ if (addr & 4) {
+ return s->latch_tmp;
+ }
+
+ switch (addr) {
+ case 0x0000:
+ /* WSBA0: Window Space Base Address Register. */
+ ret = s->pchip.win[0].base_addr;
+ break;
+ case 0x0040:
+ /* WSBA1 */
+ ret = s->pchip.win[1].base_addr;
+ break;
+ case 0x0080:
+ /* WSBA2 */
+ ret = s->pchip.win[2].base_addr;
+ break;
+ case 0x00c0:
+ /* WSBA3 */
+ ret = s->pchip.win[3].base_addr;
+ break;
+
+ case 0x0100:
+ /* WSM0: Window Space Mask Register. */
+ ret = s->pchip.win[0].mask;
+ break;
+ case 0x0140:
+ /* WSM1 */
+ ret = s->pchip.win[1].mask;
+ break;
+ case 0x0180:
+ /* WSM2 */
+ ret = s->pchip.win[2].mask;
+ break;
+ case 0x01c0:
+ /* WSM3 */
+ ret = s->pchip.win[3].mask;
+ break;
+
+ case 0x0200:
+ /* TBA0: Translated Base Address Register. */
+ ret = (uint64_t)s->pchip.win[0].translated_base_pfn << 10;
+ break;
+ case 0x0240:
+ /* TBA1 */
+ ret = (uint64_t)s->pchip.win[1].translated_base_pfn << 10;
+ break;
+ case 0x0280:
+ /* TBA2 */
+ ret = (uint64_t)s->pchip.win[2].translated_base_pfn << 10;
+ break;
+ case 0x02c0:
+ /* TBA3 */
+ ret = (uint64_t)s->pchip.win[3].translated_base_pfn << 10;
+ break;
+
+ case 0x0300:
+ /* PCTL: Pchip Control Register. */
+ ret = s->pchip.ctl;
+ break;
+ case 0x0340:
+ /* PLAT: Pchip Master Latency Register. */
+ break;
+ case 0x03c0:
+ /* PERROR: Pchip Error Register. */
+ break;
+ case 0x0400:
+ /* PERRMASK: Pchip Error Mask Register. */
+ break;
+ case 0x0440:
+ /* PERRSET: Pchip Error Set Register. */
+ break;
+ case 0x0480:
+ /* TLBIV: Translation Buffer Invalidate Virtual Register (WO). */
+ break;
+ case 0x04c0:
+ /* TLBIA: Translation Buffer Invalidate All Register (WO). */
+ break;
+ case 0x0500: /* PMONCTL */
+ case 0x0540: /* PMONCNT */
+ case 0x0800: /* SPRST */
+ break;
+
+ default:
+ cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);
+ return -1;
+ }
+
+ s->latch_tmp = ret >> 32;
+ return ret;
+}
+
+static void cchip_write(void *opaque, target_phys_addr_t addr,
+ uint64_t v32, unsigned size)
+{
+ TyphoonState *s = opaque;
+ uint64_t val, oldval, newval;
+
+ if (addr & 4) {
+ val = v32 << 32 | s->latch_tmp;
+ addr ^= 4;
+ } else {
+ s->latch_tmp = v32;
+ return;
+ }
+
+ switch (addr) {
+ case 0x0000:
+ /* CSC: Cchip System Configuration Register. */
+ /* All sorts of data here; nothing relevant RW. */
+ break;
+
+ case 0x0040:
+ /* MTR: Memory Timing Register. */
+ /* All sorts of stuff related to real DRAM. */
+ break;
+
+ case 0x0080:
+ /* MISC: Miscellaneous Register. */
+ newval = oldval = s->cchip.misc;
+ newval &= ~(val & 0x10000ff0); /* W1C fields */
+ if (val & 0x100000) {
+ newval &= ~0xff0000ull; /* ACL clears ABT and ABW */
+ } else {
+ newval |= val & 0x00f00000; /* ABT field is W1S */
+ if ((newval & 0xf0000) == 0) {
+ newval |= val & 0xf0000; /* ABW field is W1S iff zero */
+ }
+ }
+ newval |= (val & 0xf000) >> 4; /* IPREQ field sets IPINTR. */
+
+ newval &= ~0xf0000000000ull; /* WO and RW fields */
+ newval |= val & 0xf0000000000ull;
+ s->cchip.misc = newval;
+
+ /* Pass on changes to IPI and ITI state. */
+ if ((newval ^ oldval) & 0xff0) {
+ int i;
+ for (i = 0; i < 4; ++i) {
+ CPUState *env = s->cchip.cpu[i];
+ if (env) {
+ /* IPI can be either cleared or set by the write. */
+ if (newval & (1 << (i + 8))) {
+ cpu_interrupt(env, CPU_INTERRUPT_SMP);
+ } else {
+ cpu_reset_interrupt(env, CPU_INTERRUPT_SMP);
+ }
+
+ /* ITI can only be cleared by the write. */
+ if ((newval & (1 << (i + 4))) == 0) {
+ cpu_reset_interrupt(env, CPU_INTERRUPT_TIMER);
+ }
+ }
+ }
+ }
+ break;
+
+ case 0x00c0:
+ /* MPD: Memory Presence Detect Register. */
+ break;
+
+ case 0x0100: /* AAR0 */
+ case 0x0140: /* AAR1 */
+ case 0x0180: /* AAR2 */
+ case 0x01c0: /* AAR3 */
+ /* AAR: Array Address Register. */
+ /* All sorts of information about DRAM. */
+ break;
+
+ case 0x0200: /* DIM0 */
+ /* DIM: Device Interrupt Mask Register, CPU0. */
+ s->cchip.dim[0] = val;
+ cpu_irq_change(s->cchip.cpu[0], val & s->cchip.drir);
+ break;
+ case 0x0240: /* DIM1 */
+ /* DIM: Device Interrupt Mask Register, CPU1. */
+ s->cchip.dim[0] = val;
+ cpu_irq_change(s->cchip.cpu[1], val & s->cchip.drir);
+ break;
+
+ case 0x0280: /* DIR0 (RO) */
+ case 0x02c0: /* DIR1 (RO) */
+ case 0x0300: /* DRIR (RO) */
+ break;
+
+ case 0x0340:
+ /* PRBEN: Probe Enable Register. */
+ break;
+
+ case 0x0380: /* IIC0 */
+ s->cchip.iic[0] = val & 0xffffff;
+ break;
+ case 0x03c0: /* IIC1 */
+ s->cchip.iic[1] = val & 0xffffff;
+ break;
+
+ case 0x0400: /* MPR0 */
+ case 0x0440: /* MPR1 */
+ case 0x0480: /* MPR2 */
+ case 0x04c0: /* MPR3 */
+ /* MPR: Memory Programming Register. */
+ break;
+
+ case 0x0580:
+ /* TTR: TIGbus Timing Register. */
+ /* All sorts of stuff related to interrupt delivery timings. */
+ break;
+ case 0x05c0:
+ /* TDR: TIGbug Device Timing Register. */
+ break;
+
+ case 0x0600:
+ /* DIM2: Device Interrupt Mask Register, CPU2. */
+ s->cchip.dim[2] = val;
+ cpu_irq_change(s->cchip.cpu[2], val & s->cchip.drir);
+ break;
+ case 0x0640:
+ /* DIM3: Device Interrupt Mask Register, CPU3. */
+ s->cchip.dim[3] = val;
+ cpu_irq_change(s->cchip.cpu[3], val & s->cchip.drir);
+ break;
+
+ case 0x0680: /* DIR2 (RO) */
+ case 0x06c0: /* DIR3 (RO) */
+ break;
+
+ case 0x0700: /* IIC2 */
+ s->cchip.iic[2] = val & 0xffffff;
+ break;
+ case 0x0740: /* IIC3 */
+ s->cchip.iic[3] = val & 0xffffff;
+ break;
+
+ case 0x0780:
+ /* PWR: Power Management Control. */
+ break;
+
+ case 0x0c00: /* CMONCTLA */
+ case 0x0c40: /* CMONCTLB */
+ case 0x0c80: /* CMONCNT01 */
+ case 0x0cc0: /* CMONCNT23 */
+ break;
+
+ default:
+ cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);
+ return;
+ }
+}
+
+static void dchip_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
+{
+ /* Skip this. It's all related to DRAM timing and setup. */
+}
+
+static void pchip_write(void *opaque, target_phys_addr_t addr,
+ uint64_t v32, unsigned size)
+{
+ TyphoonState *s = opaque;
+ uint64_t val, oldval;
+
+ if (addr & 4) {
+ val = v32 << 32 | s->latch_tmp;
+ addr ^= 4;
+ } else {
+ s->latch_tmp = v32;
+ return;
+ }
+
+ switch (addr) {
+ case 0x0000:
+ /* WSBA0: Window Space Base Address Register. */
+ s->pchip.win[0].base_addr = val;
+ break;
+ case 0x0040:
+ /* WSBA1 */
+ s->pchip.win[1].base_addr = val;
+ break;
+ case 0x0080:
+ /* WSBA2 */
+ s->pchip.win[2].base_addr = val;
+ break;
+ case 0x00c0:
+ /* WSBA3 */
+ s->pchip.win[3].base_addr = val;
+ break;
+
+ case 0x0100:
+ /* WSM0: Window Space Mask Register. */
+ s->pchip.win[0].mask = val;
+ break;
+ case 0x0140:
+ /* WSM1 */
+ s->pchip.win[1].mask = val;
+ break;
+ case 0x0180:
+ /* WSM2 */
+ s->pchip.win[2].mask = val;
+ break;
+ case 0x01c0:
+ /* WSM3 */
+ s->pchip.win[3].mask = val;
+ break;
+
+ case 0x0200:
+ /* TBA0: Translated Base Address Register. */
+ s->pchip.win[0].translated_base_pfn = val >> 10;
+ break;
+ case 0x0240:
+ /* TBA1 */
+ s->pchip.win[1].translated_base_pfn = val >> 10;
+ break;
+ case 0x0280:
+ /* TBA2 */
+ s->pchip.win[2].translated_base_pfn = val >> 10;
+ break;
+ case 0x02c0:
+ /* TBA3 */
+ s->pchip.win[3].translated_base_pfn = val >> 10;
+ break;
+
+ case 0x0300:
+ /* PCTL: Pchip Control Register. */
+ oldval = s->pchip.ctl;
+ oldval &= ~0x00001cff0fc7ffull; /* RW fields */
+ oldval |= val & 0x00001cff0fc7ffull;
+
+ s->pchip.ctl = oldval;
+ break;
+
+ case 0x0340:
+ /* PLAT: Pchip Master Latency Register. */
+ break;
+ case 0x03c0:
+ /* PERROR: Pchip Error Register. */
+ break;
+ case 0x0400:
+ /* PERRMASK: Pchip Error Mask Register. */
+ break;
+ case 0x0440:
+ /* PERRSET: Pchip Error Set Register. */
+ break;
+
+ case 0x0480:
+ /* TLBIV: Translation Buffer Invalidate Virtual Register. */
+ break;
+
+ case 0x04c0:
+ /* TLBIA: Translation Buffer Invalidate All Register (WO). */
+ break;
+
+ case 0x0500:
+ /* PMONCTL */
+ case 0x0540:
+ /* PMONCNT */
+ case 0x0800:
+ /* SPRST */
+ break;
+
+ default:
+ cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);
+ return;
+ }
+}
+
+static const MemoryRegionOps cchip_ops = {
+ .read = cchip_read,
+ .write = cchip_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4, /* ??? Should be 8. */
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static const MemoryRegionOps dchip_ops = {
+ .read = dchip_read,
+ .write = dchip_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4, /* ??? Should be 8. */
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
+};
+
+static const MemoryRegionOps pchip_ops = {
+ .read = pchip_read,
+ .write = pchip_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4, /* ??? Should be 8. */
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void typhoon_set_irq(void *opaque, int irq, int level)
+{
+ TyphoonState *s = opaque;
+ uint64_t drir;
+ int i;
+
+ /* Set/Reset the bit in CCHIP.DRIR based on IRQ+LEVEL. */
+ drir = s->cchip.drir;
+ if (level) {
+ drir |= 1ull << irq;
+ } else {
+ drir &= ~(1ull << irq);
+ }
+ s->cchip.drir = drir;
+
+ for (i = 0; i < 4; ++i) {
+ cpu_irq_change(s->cchip.cpu[i], s->cchip.dim[i] & drir);
+ }
+}
+
+static void typhoon_set_isa_irq(void *opaque, int irq, int level)
+{
+ typhoon_set_irq(opaque, 55, level);
+}
+
+static void typhoon_set_timer_irq(void *opaque, int irq, int level)
+{
+ TyphoonState *s = opaque;
+ int i;
+
+ /* Thankfully, the mc146818rtc code doesn't track the IRQ state,
+ and so we don't have to worry about missing interrupts just
+ because we never actually ACK the interrupt. Just ignore any
+ case of the interrupt level going low. */
+ if (level == 0) {
+ return;
+ }
+
+ /* Deliver the interrupt to each CPU, considering each CPU's IIC. */
+ for (i = 0; i < 4; ++i) {
+ CPUState *env = s->cchip.cpu[i];
+ if (env) {
+ uint32_t iic = s->cchip.iic[i];
+
+ /* ??? The verbage in Section 10.2.2.10 isn't 100% clear.
+ Bit 24 is the OverFlow bit, RO, and set when the count
+ decrements past 0. When is OF cleared? My guess is that
+ OF is actually cleared when the IIC is written, and that
+ the ICNT field always decrements. At least, that's an
+ interpretation that makes sense, and "allows the CPU to
+ determine exactly how mant interval timer ticks were
+ skipped". At least within the next 4M ticks... */
+
+ iic = ((iic - 1) & 0x1ffffff) | (iic & 0x1000000);
+ s->cchip.iic[i] = iic;
+
+ if (iic & 0x1000000) {
+ /* Set the ITI bit for this cpu. */
+ s->cchip.misc |= 1 << (i + 4);
+ /* And signal the interrupt. */
+ cpu_interrupt(env, CPU_INTERRUPT_TIMER);
+ }
+ }
+ }
+}
+
+PCIBus *typhoon_init(ram_addr_t ram_size, qemu_irq *p_rtc_irq,
+ CPUState *cpus[4], pci_map_irq_fn sys_map_irq)
+{
+ const uint64_t MB = 1024 * 1024;
+ const uint64_t GB = 1024 * MB;
+ MemoryRegion *addr_space = get_system_memory();
+ MemoryRegion *addr_space_io = get_system_io();
+ DeviceState *dev;
+ PCIHostState *p;
+ TyphoonState *s;
+ PCIBus *b;
+
+ dev = qdev_create(NULL, "typhoon-pcihost");
+ qdev_init_nofail(dev);
+
+ p = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
+ s = container_of(p, TyphoonState, host);
+
+ /* Remember the CPUs so that we can deliver interrupts to them. */
+ memcpy(s->cchip.cpu, cpus, 4 * sizeof(CPUState *));
+
+ *p_rtc_irq = *qemu_allocate_irqs(typhoon_set_timer_irq, s, 1);
+
+ /* Main memory region, 0x00.0000.0000. Real hardware supports 32GB,
+ but the address space hole reserved at this point is 8TB. */
+ memory_region_init_ram(&s->ram_region, NULL, "ram", ram_size);
+ memory_region_add_subregion(addr_space, 0, &s->ram_region);
+
+ /* TIGbus, 0x801.0000.0000, 1GB. */
+ /* ??? The TIGbus is used for delivering interrupts, and access to
+ the flash ROM. I'm not sure that we need to implement it at all. */
+
+ /* Pchip0 CSRs, 0x801.8000.0000, 256MB. */
+ memory_region_init_io(&s->pchip.region, &pchip_ops, s, "pchip0", 256*MB);
+ memory_region_add_subregion(addr_space, 0x80180000000, &s->pchip.region);
+
+ /* Cchip CSRs, 0x801.A000.0000, 256MB. */
+ memory_region_init_io(&s->cchip.region, &cchip_ops, s, "cchip0", 256*MB);
+ memory_region_add_subregion(addr_space, 0x801a0000000, &s->cchip.region);
+
+ /* Dchip CSRs, 0x801.B000.0000, 256MB. */
+ memory_region_init_io(&s->dchip_region, &dchip_ops, s, "dchip0", 256*MB);
+ memory_region_add_subregion(addr_space, 0x801b0000000, &s->dchip_region);
+
+ /* Pchip0 PCI memory, 0x800.0000.0000, 4GB. */
+ memory_region_init(&s->pchip.reg_mem, "pci0-mem", 4*GB);
+ memory_region_add_subregion(addr_space, 0x80000000000, &s->pchip.reg_mem);
+
+ /* Pchip0 PCI I/O, 0x801.FC00.0000, 32MB. */
+ /* ??? Ideally we drop the "system" i/o space on the floor and give the
+ PCI subsystem the full address space reserved by the chipset.
+ We can't do that until the MEM and IO paths in memory.c are unified. */
+ memory_region_init_io(&s->pchip.reg_io, &alpha_pci_bw_io_ops, NULL,
+ "pci0-io", 32*MB);
+ memory_region_add_subregion(addr_space, 0x801fc000000, &s->pchip.reg_io);
+
+ b = pci_register_bus(&s->host.busdev.qdev, "pci",
+ typhoon_set_irq, sys_map_irq, s,
+ &s->pchip.reg_mem, addr_space_io, 0, 64);
+ s->host.bus = b;
+
+ /* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */
+ memory_region_init_io(&s->pchip.reg_iack, &alpha_pci_iack_ops, b,
+ "pci0-iack", 64*MB);
+ memory_region_add_subregion(addr_space, 0x801f8000000, &s->pchip.reg_iack);
+
+ /* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB. */
+ memory_region_init_io(&s->pchip.reg_conf, &alpha_pci_conf1_ops, b,
+ "pci0-conf", 16*MB);
+ memory_region_add_subregion(addr_space, 0x801fe000000, &s->pchip.reg_conf);
+
+ /* For the record, these are the mappings for the second PCI bus.
+ We can get away with not implementing them because we indicate
+ via the Cchip.CSC<PIP> bit that Pchip1 is not present. */
+ /* Pchip1 PCI memory, 0x802.0000.0000, 4GB. */
+ /* Pchip1 CSRs, 0x802.8000.0000, 256MB. */
+ /* Pchip1 PCI special/interrupt acknowledge, 0x802.F800.0000, 64MB. */
+ /* Pchip1 PCI I/O, 0x802.FC00.0000, 32MB. */
+ /* Pchip1 PCI configuration, 0x802.FE00.0000, 16MB. */
+
+ /* Init the ISA bus. */
+ /* ??? Technically there should be a cy82c693ub pci-isa bridge. */
+ {
+ qemu_irq isa_pci_irq, *isa_irqs;
+
+ isa_bus_new(NULL);
+ isa_pci_irq = *qemu_allocate_irqs(typhoon_set_isa_irq, s, 1);
+ isa_irqs = i8259_init(isa_pci_irq);
+ isa_bus_irqs(isa_irqs);
+ }
+
+ return b;
+}
+
+static int typhoon_pcihost_init(SysBusDevice *dev)
+{
+ return 0;
+}
+
+static SysBusDeviceInfo typhoon_pcihost_info = {
+ .init = typhoon_pcihost_init,
+ .qdev.name = "typhoon-pcihost",
+ .qdev.size = sizeof(TyphoonState),
+ .qdev.no_user = 1
+};
+
+static void typhoon_register(void)
+{
+ sysbus_register_withprop(&typhoon_pcihost_info);
+}
+device_init(typhoon_register);
--
1.7.4.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Qemu-devel] [PATCH 3/6] target-alpha: Add CLIPPER emulation.
2011-08-25 21:45 [Qemu-devel] [PULL][PATCH 0/6] Alpha system emulation, v9 Richard Henderson
2011-08-25 21:45 ` [Qemu-devel] [PATCH 1/6] target-alpha: Add custom PALcode image for CLIPPER emulation Richard Henderson
2011-08-25 21:45 ` [Qemu-devel] [PATCH 2/6] target-alpha: Add " Richard Henderson
@ 2011-08-25 21:45 ` Richard Henderson
2011-08-25 21:45 ` [Qemu-devel] [PATCH 4/6] target-alpha: Implement WAIT IPR Richard Henderson
` (3 subsequent siblings)
6 siblings, 0 replies; 17+ messages in thread
From: Richard Henderson @ 2011-08-25 21:45 UTC (permalink / raw)
To: qemu-devel
This is a DP264 variant, SMP capable, no unusual hardware present.
The emulation does not currently include any PCI IOMMU code.
Hopefully the generic support for that can be merged to HEAD soon.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
Makefile.target | 1 +
default-configs/alpha-softmmu.mak | 2 +
hw/alpha_dp264.c | 177 +++++++++++++++++++++++++++++++++++++
hw/alpha_pci.c | 134 ++++++++++++++++++++++++++++
hw/alpha_sys.h | 24 +++++
5 files changed, 338 insertions(+), 0 deletions(-)
create mode 100644 hw/alpha_dp264.c
create mode 100644 hw/alpha_pci.c
create mode 100644 hw/alpha_sys.h
diff --git a/Makefile.target b/Makefile.target
index e280bf6..7e8a6b4 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -372,6 +372,7 @@ obj-s390x-y = s390-virtio-bus.o s390-virtio.o
obj-alpha-y = i8259.o mc146818rtc.o
obj-alpha-y += vga.o cirrus_vga.o
+obj-alpha-y += alpha_pci.o alpha_dp264.o alpha_typhoon.o
main.o: QEMU_CFLAGS+=$(GPROF_CFLAGS)
diff --git a/default-configs/alpha-softmmu.mak b/default-configs/alpha-softmmu.mak
index abadcff..be86d0c 100644
--- a/default-configs/alpha-softmmu.mak
+++ b/default-configs/alpha-softmmu.mak
@@ -3,7 +3,9 @@
include pci.mak
CONFIG_SERIAL=y
CONFIG_I8254=y
+CONFIG_PCKBD=y
CONFIG_VGA_PCI=y
CONFIG_IDE_CORE=y
CONFIG_IDE_QDEV=y
CONFIG_VMWARE_VGA=y
+CONFIG_IDE_CMD646=y
diff --git a/hw/alpha_dp264.c b/hw/alpha_dp264.c
new file mode 100644
index 0000000..7c36b21
--- /dev/null
+++ b/hw/alpha_dp264.c
@@ -0,0 +1,177 @@
+/*
+ * QEMU Alpha DP264/CLIPPER hardware system emulator.
+ *
+ * Choose CLIPPER IRQ mappings over, say, DP264, MONET, or WEBBRICK
+ * variants because CLIPPER doesn't have an SMC669 SuperIO controler
+ * that we need to emulate as well.
+ */
+
+#include "hw.h"
+#include "elf.h"
+#include "loader.h"
+#include "boards.h"
+#include "alpha_sys.h"
+#include "sysemu.h"
+#include "mc146818rtc.h"
+#include "ide.h"
+
+#define MAX_IDE_BUS 2
+
+static uint64_t cpu_alpha_superpage_to_phys(void *opaque, uint64_t addr)
+{
+ if (((addr >> 41) & 3) == 2) {
+ addr &= 0xffffffffffull;
+ }
+ return addr;
+}
+
+/* Note that there are at least 3 viewpoints of IRQ numbers on Alpha systems.
+ (0) The dev_irq_n lines into the cpu, which we totally ignore,
+ (1) The DRIR lines in the typhoon chipset,
+ (2) The "vector" aka mangled interrupt number reported by SRM PALcode,
+ (3) The interrupt number assigned by the kernel.
+ The following function is concerned with (1) only. */
+
+static int clipper_pci_map_irq(PCIDevice *d, int irq_num)
+{
+ int slot = d->devfn >> 3;
+
+ assert(irq_num >= 0 && irq_num <= 3);
+
+ return (slot + 1) * 4 + irq_num;
+}
+
+static void clipper_init(ram_addr_t ram_size,
+ const char *boot_device,
+ const char *kernel_filename,
+ const char *kernel_cmdline,
+ const char *initrd_filename,
+ const char *cpu_model)
+{
+ CPUState *cpus[4];
+ PCIBus *pci_bus;
+ qemu_irq rtc_irq;
+ long size, i;
+ const char *palcode_filename;
+ uint64_t palcode_entry, palcode_low, palcode_high;
+ uint64_t kernel_entry, kernel_low, kernel_high;
+
+ /* Create up to 4 cpus. */
+ memset(cpus, 0, sizeof(cpus));
+ for (i = 0; i < smp_cpus; ++i) {
+ cpus[i] = cpu_init(cpu_model ? cpu_model : "ev67");
+ }
+
+ cpus[0]->trap_arg0 = ram_size;
+ cpus[0]->trap_arg1 = 0;
+ cpus[0]->trap_arg2 = smp_cpus;
+
+ /* Init the chipset. */
+ pci_bus = typhoon_init(ram_size, &rtc_irq, cpus, clipper_pci_map_irq);
+
+ rtc_init(1980, rtc_irq);
+ pit_init(0x40, 0);
+ isa_create_simple("i8042");
+
+ /* VGA setup. Don't bother loading the bios. */
+ alpha_pci_vga_setup(pci_bus);
+
+ /* Serial code setup. */
+ for (i = 0; i < MAX_SERIAL_PORTS; ++i) {
+ if (serial_hds[i]) {
+ serial_isa_init(i, serial_hds[i]);
+ }
+ }
+
+ /* Network setup. e1000 is good enough, failing Tulip support. */
+ for (i = 0; i < nb_nics; i++) {
+ pci_nic_init_nofail(&nd_table[i], "e1000", NULL);
+ }
+
+ /* IDE disk setup. */
+ {
+ DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
+ ide_drive_get(hd, MAX_IDE_BUS);
+
+ pci_cmd646_ide_init(pci_bus, hd, 0);
+ }
+
+ /* Load PALcode. Given that this is not "real" cpu palcode,
+ but one explicitly written for the emulation, we might as
+ well load it directly from and ELF image. */
+ palcode_filename = (bios_name ? bios_name : "palcode-clipper");
+ palcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, palcode_filename);
+ if (palcode_filename == NULL) {
+ hw_error("no palcode provided\n");
+ exit(1);
+ }
+ size = load_elf(palcode_filename, cpu_alpha_superpage_to_phys,
+ NULL, &palcode_entry, &palcode_low, &palcode_high,
+ 0, EM_ALPHA, 0);
+ if (size < 0) {
+ hw_error("could not load palcode '%s'\n", palcode_filename);
+ exit(1);
+ }
+
+ /* Start all cpus at the PALcode RESET entry point. */
+ for (i = 0; i < smp_cpus; ++i) {
+ cpus[i]->pal_mode = 1;
+ cpus[i]->pc = palcode_entry;
+ cpus[i]->palbr = palcode_entry;
+ }
+
+ /* Load a kernel. */
+ if (kernel_filename) {
+ uint64_t param_offset;
+
+ size = load_elf(kernel_filename, cpu_alpha_superpage_to_phys,
+ NULL, &kernel_entry, &kernel_low, &kernel_high,
+ 0, EM_ALPHA, 0);
+ if (size < 0) {
+ hw_error("could not load kernel '%s'\n", kernel_filename);
+ exit(1);
+ }
+
+ cpus[0]->trap_arg1 = kernel_entry;
+
+ param_offset = kernel_low - 0x6000;
+
+ if (kernel_cmdline) {
+ pstrcpy_targphys("cmdline", param_offset, 0x100, kernel_cmdline);
+ }
+
+ if (initrd_filename) {
+ long initrd_base, initrd_size;
+
+ initrd_size = get_image_size(initrd_filename);
+ if (initrd_size < 0) {
+ hw_error("could not load initial ram disk '%s'\n",
+ initrd_filename);
+ exit(1);
+ }
+
+ /* Put the initrd image as high in memory as possible. */
+ initrd_base = (ram_size - initrd_size) & TARGET_PAGE_MASK;
+ load_image_targphys(initrd_filename, initrd_base,
+ ram_size - initrd_base);
+
+ stq_phys(param_offset + 0x100, initrd_base + 0xfffffc0000000000UL);
+ stq_phys(param_offset + 0x108, initrd_size);
+ }
+ }
+}
+
+static QEMUMachine clipper_machine = {
+ .name = "clipper",
+ .desc = "Alpha DP264/CLIPPER",
+ .init = clipper_init,
+ .max_cpus = 4,
+ .is_default = 1,
+};
+
+static void clipper_machine_init(void)
+{
+ qemu_register_machine(&clipper_machine);
+}
+
+machine_init(clipper_machine_init);
diff --git a/hw/alpha_pci.c b/hw/alpha_pci.c
new file mode 100644
index 0000000..e975702
--- /dev/null
+++ b/hw/alpha_pci.c
@@ -0,0 +1,134 @@
+/*
+ * QEMU Alpha PCI support functions.
+ *
+ * Some of this isn't very Alpha specific at all.
+ *
+ * ??? Sparse memory access not implemented.
+ */
+
+#include "config.h"
+#include "alpha_sys.h"
+#include "qemu-log.h"
+#include "sysemu.h"
+#include "vmware_vga.h"
+
+
+/* PCI IO reads/writes, to byte-word addressable memory. */
+/* ??? Doesn't handle multiple PCI busses. */
+
+static uint64_t bw_io_read(void *opaque, target_phys_addr_t addr, unsigned size)
+{
+ switch (size) {
+ case 1:
+ return cpu_inb(addr);
+ case 2:
+ return cpu_inw(addr);
+ case 4:
+ return cpu_inl(addr);
+ }
+ abort();
+}
+
+static void bw_io_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
+{
+ switch (size) {
+ case 1:
+ cpu_outb(addr, val);
+ break;
+ case 2:
+ cpu_outw(addr, val);
+ break;
+ case 4:
+ cpu_outl(addr, val);
+ break;
+ default:
+ abort();
+ }
+}
+
+const MemoryRegionOps alpha_pci_bw_io_ops = {
+ .read = bw_io_read,
+ .write = bw_io_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+/* PCI config space reads/writes, to byte-word addressable memory. */
+static uint64_t bw_conf1_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
+{
+ PCIBus *b = opaque;
+ return pci_data_read(b, addr, size);
+}
+
+static void bw_conf1_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
+{
+ PCIBus *b = opaque;
+ pci_data_write(b, addr, val, size);
+}
+
+const MemoryRegionOps alpha_pci_conf1_ops = {
+ .read = bw_conf1_read,
+ .write = bw_conf1_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+/* PCI/EISA Interrupt Acknowledge Cycle. */
+
+static uint64_t iack_read(void *opaque, target_phys_addr_t addr, unsigned size)
+{
+ return pic_read_irq(isa_pic);
+}
+
+static void special_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
+{
+ qemu_log("pci: special write cycle");
+}
+
+const MemoryRegionOps alpha_pci_iack_ops = {
+ .read = iack_read,
+ .write = special_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+\f
+void alpha_pci_vga_setup(PCIBus *pci_bus)
+{
+ switch (vga_interface_type) {
+#ifdef CONFIG_SPICE
+ case VGA_QXL:
+ pci_create_simple(pci_bus, -1, "qxl-vga");
+ return;
+#endif
+ case VGA_CIRRUS:
+ pci_cirrus_vga_init(pci_bus);
+ return;
+ case VGA_VMWARE:
+ if (pci_vmsvga_init(pci_bus)) {
+ return;
+ }
+ break;
+ }
+ /* If VGA is enabled at all, and one of the above didn't work, then
+ fallback to Standard VGA. */
+ if (vga_interface_type != VGA_NONE) {
+ pci_vga_init(pci_bus);
+ }
+}
diff --git a/hw/alpha_sys.h b/hw/alpha_sys.h
new file mode 100644
index 0000000..13f0177
--- /dev/null
+++ b/hw/alpha_sys.h
@@ -0,0 +1,24 @@
+/* Alpha cores and system support chips. */
+
+#ifndef HW_ALPHA_H
+#define HW_ALPHA_H 1
+
+#include "pci.h"
+#include "pci_host.h"
+#include "ide.h"
+#include "net.h"
+#include "pc.h"
+#include "usb-ohci.h"
+#include "irq.h"
+
+
+PCIBus *typhoon_init(ram_addr_t, qemu_irq *, CPUState *[4], pci_map_irq_fn);
+
+/* alpha_pci.c. */
+extern const MemoryRegionOps alpha_pci_bw_io_ops;
+extern const MemoryRegionOps alpha_pci_conf1_ops;
+extern const MemoryRegionOps alpha_pci_iack_ops;
+
+void alpha_pci_vga_setup(PCIBus *pci_bus);
+
+#endif
--
1.7.4.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Qemu-devel] [PATCH 4/6] target-alpha: Implement WAIT IPR.
2011-08-25 21:45 [Qemu-devel] [PULL][PATCH 0/6] Alpha system emulation, v9 Richard Henderson
` (2 preceding siblings ...)
2011-08-25 21:45 ` [Qemu-devel] [PATCH 3/6] " Richard Henderson
@ 2011-08-25 21:45 ` Richard Henderson
2011-08-25 21:45 ` [Qemu-devel] [PATCH 5/6] target-alpha: Implement HALT IPR Richard Henderson
` (2 subsequent siblings)
6 siblings, 0 replies; 17+ messages in thread
From: Richard Henderson @ 2011-08-25 21:45 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-alpha/translate.c | 31 +++++++++++++++++++++----------
1 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 1e224a2..86343df 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -1617,9 +1617,10 @@ static void gen_mfpr(int ra, int regno)
}
}
-static void gen_mtpr(int rb, int regno)
+static ExitStatus gen_mtpr(DisasContext *ctx, int rb, int regno)
{
TCGv tmp;
+ int data;
if (rb == 31) {
tmp = tcg_const_i64(0);
@@ -1627,19 +1628,27 @@ static void gen_mtpr(int rb, int regno)
tmp = cpu_ir[rb];
}
- /* These two register numbers perform a TLB cache flush. Thankfully we
- can only do this inside PALmode, which means that the current basic
- block cannot be affected by the change in mappings. */
- if (regno == 255) {
+ switch (regno) {
+ case 255:
/* TBIA */
gen_helper_tbia();
- } else if (regno == 254) {
+ break;
+
+ case 254:
/* TBIS */
gen_helper_tbis(tmp);
- } else {
+ break;
+
+ case 253:
+ /* WAIT */
+ tmp = tcg_const_i64(1);
+ tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUState, halted));
+ return gen_excp(ctx, EXCP_HLT, 0);
+
+ default:
/* The basic registers are data only, and unknown registers
are read-zero, write-ignore. */
- int data = cpu_pr_data(regno);
+ data = cpu_pr_data(regno);
if (data != 0) {
if (data & PR_BYTE) {
tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE);
@@ -1649,11 +1658,14 @@ static void gen_mtpr(int rb, int regno)
tcg_gen_st_i64(tmp, cpu_env, data);
}
}
+ break;
}
if (rb == 31) {
tcg_temp_free(tmp);
}
+
+ return NO_EXIT;
}
#endif /* !USER_ONLY*/
@@ -3053,8 +3065,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
/* HW_MTPR (PALcode) */
#ifndef CONFIG_USER_ONLY
if (ctx->tb->flags & TB_FLAGS_PAL_MODE) {
- gen_mtpr(rb, insn & 0xffff);
- break;
+ return gen_mtpr(ctx, rb, insn & 0xffff);
}
#endif
goto invalid_opc;
--
1.7.4.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Qemu-devel] [PATCH 5/6] target-alpha: Implement HALT IPR.
2011-08-25 21:45 [Qemu-devel] [PULL][PATCH 0/6] Alpha system emulation, v9 Richard Henderson
` (3 preceding siblings ...)
2011-08-25 21:45 ` [Qemu-devel] [PATCH 4/6] target-alpha: Implement WAIT IPR Richard Henderson
@ 2011-08-25 21:45 ` Richard Henderson
2011-08-25 21:45 ` [Qemu-devel] [PATCH 6/6] target-alpha: Add high-resolution access to wall clock and an alarm Richard Henderson
2011-08-25 21:59 ` [Qemu-devel] [PULL][PATCH 0/6] Alpha system emulation, v9 Richard Henderson
6 siblings, 0 replies; 17+ messages in thread
From: Richard Henderson @ 2011-08-25 21:45 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-alpha/helper.h | 1 +
target-alpha/op_helper.c | 10 ++++++++++
target-alpha/translate.c | 5 +++++
3 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index 2dec57e..c352c24 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -113,6 +113,7 @@ DEF_HELPER_2(stq_c_phys, i64, i64, i64)
DEF_HELPER_FLAGS_0(tbia, TCG_CALL_CONST, void)
DEF_HELPER_FLAGS_1(tbis, TCG_CALL_CONST, void, i64)
+DEF_HELPER_1(halt, void, i64);
#endif
#include "def-helper.h"
diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
index 38be234..db5b9e7 100644
--- a/target-alpha/op_helper.c
+++ b/target-alpha/op_helper.c
@@ -22,6 +22,7 @@
#include "host-utils.h"
#include "softfloat.h"
#include "helper.h"
+#include "sysemu.h"
#include "qemu-timer.h"
#define FP_STATUS (env->fp_status)
@@ -1218,6 +1219,15 @@ void helper_tbis(uint64_t p)
{
tlb_flush_page(env, p);
}
+
+void helper_halt(uint64_t restart)
+{
+ if (restart) {
+ qemu_system_reset_request();
+ } else {
+ qemu_system_shutdown_request();
+ }
+}
#endif
/*****************************************************************************/
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 86343df..842f915 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -1645,6 +1645,11 @@ static ExitStatus gen_mtpr(DisasContext *ctx, int rb, int regno)
tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUState, halted));
return gen_excp(ctx, EXCP_HLT, 0);
+ case 252:
+ /* HALT */
+ gen_helper_halt(tmp);
+ return EXIT_PC_STALE;
+
default:
/* The basic registers are data only, and unknown registers
are read-zero, write-ignore. */
--
1.7.4.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Qemu-devel] [PATCH 6/6] target-alpha: Add high-resolution access to wall clock and an alarm.
2011-08-25 21:45 [Qemu-devel] [PULL][PATCH 0/6] Alpha system emulation, v9 Richard Henderson
` (4 preceding siblings ...)
2011-08-25 21:45 ` [Qemu-devel] [PATCH 5/6] target-alpha: Implement HALT IPR Richard Henderson
@ 2011-08-25 21:45 ` Richard Henderson
2011-08-26 3:51 ` Peter Maydell
2011-08-25 21:59 ` [Qemu-devel] [PULL][PATCH 0/6] Alpha system emulation, v9 Richard Henderson
6 siblings, 1 reply; 17+ messages in thread
From: Richard Henderson @ 2011-08-25 21:45 UTC (permalink / raw)
To: qemu-devel
The alarm is a fully general one-shot time comparator, which will be
usable under Linux as a hrtimer source. It's much more flexible than
the RTC source available on real hardware.
The wall clock allows the guest access to the host timekeeping. Much
like the KVM wall clock source for other guests.
Both are accessed via the PALcode Cserve entry point.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
hw/alpha_typhoon.c | 21 ++++++++++++++++++++-
target-alpha/cpu.h | 4 ++++
target-alpha/helper.h | 4 ++++
target-alpha/op_helper.c | 15 +++++++++++++++
target-alpha/translate.c | 14 ++++++++++++++
5 files changed, 57 insertions(+), 1 deletions(-)
diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c
index 3637efc..3d30e0e 100644
--- a/hw/alpha_typhoon.c
+++ b/hw/alpha_typhoon.c
@@ -681,6 +681,16 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level)
}
}
+static void typhoon_alarm_timer(void *opaque)
+{
+ TyphoonState *s = (TyphoonState *)((uintptr_t)opaque & ~3);
+ int cpu = (uintptr_t)opaque & 3;
+
+ /* Set the ITI bit for this cpu. */
+ s->cchip.misc |= 1 << (cpu + 4);
+ cpu_interrupt(s->cchip.cpu[cpu], CPU_INTERRUPT_TIMER);
+}
+
PCIBus *typhoon_init(ram_addr_t ram_size, qemu_irq *p_rtc_irq,
CPUState *cpus[4], pci_map_irq_fn sys_map_irq)
{
@@ -692,6 +702,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, qemu_irq *p_rtc_irq,
PCIHostState *p;
TyphoonState *s;
PCIBus *b;
+ int i;
dev = qdev_create(NULL, "typhoon-pcihost");
qdev_init_nofail(dev);
@@ -700,7 +711,15 @@ PCIBus *typhoon_init(ram_addr_t ram_size, qemu_irq *p_rtc_irq,
s = container_of(p, TyphoonState, host);
/* Remember the CPUs so that we can deliver interrupts to them. */
- memcpy(s->cchip.cpu, cpus, 4 * sizeof(CPUState *));
+ for (i = 0; i < 4; i++) {
+ CPUState *env = cpus[i];
+ s->cchip.cpu[i] = env;
+ if (env) {
+ env->alarm_timer = qemu_new_timer_ns(rtc_clock,
+ typhoon_alarm_timer,
+ (void *)((uintptr_t)s + i));
+ }
+ }
*p_rtc_irq = *qemu_allocate_irqs(typhoon_set_timer_irq, s, 1);
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index c2e7bb3..9d61d45 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -265,6 +265,10 @@ struct CPUAlphaState {
uint64_t scratch[24];
#endif
+ /* This alarm doesn't exist in real hardware; we wish it did. */
+ struct QEMUTimer *alarm_timer;
+ uint64_t alarm_expire;
+
#if TARGET_LONG_BITS > HOST_LONG_BITS
/* temporary fixed-point registers
* used to emulate 64 bits target on 32 bits hosts
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index c352c24..b693cee 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -113,7 +113,11 @@ DEF_HELPER_2(stq_c_phys, i64, i64, i64)
DEF_HELPER_FLAGS_0(tbia, TCG_CALL_CONST, void)
DEF_HELPER_FLAGS_1(tbis, TCG_CALL_CONST, void, i64)
+
DEF_HELPER_1(halt, void, i64);
+
+DEF_HELPER_FLAGS_0(get_time, TCG_CALL_CONST, i64)
+DEF_HELPER_FLAGS_1(set_alarm, TCG_CALL_CONST, void, i64)
#endif
#include "def-helper.h"
diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
index db5b9e7..6832163 100644
--- a/target-alpha/op_helper.c
+++ b/target-alpha/op_helper.c
@@ -1228,6 +1228,21 @@ void helper_halt(uint64_t restart)
qemu_system_shutdown_request();
}
}
+
+uint64_t helper_get_time(void)
+{
+ return qemu_get_clock_ns(rtc_clock);
+}
+
+void helper_set_alarm(uint64_t expire)
+{
+ if (expire) {
+ env->alarm_expire = expire;
+ qemu_mod_timer(env->alarm_timer, expire);
+ } else {
+ qemu_del_timer(env->alarm_timer);
+ }
+}
#endif
/*****************************************************************************/
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 842f915..37f2f20 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -1590,6 +1590,9 @@ static int cpu_pr_data(int pr)
return offsetof(CPUAlphaState, shadow[pr - 32]);
case 40 ... 63:
return offsetof(CPUAlphaState, scratch[pr - 40]);
+
+ case 251:
+ return offsetof(CPUAlphaState, alarm_expire);
}
return 0;
}
@@ -1604,6 +1607,12 @@ static void gen_mfpr(int ra, int regno)
return;
}
+ if (regno == 250) {
+ /* WALL_TIME */
+ gen_helper_get_time(cpu_ir[ra]);
+ return;
+ }
+
/* The basic registers are data only, and unknown registers
are read-zero, write-ignore. */
if (data == 0) {
@@ -1650,6 +1659,11 @@ static ExitStatus gen_mtpr(DisasContext *ctx, int rb, int regno)
gen_helper_halt(tmp);
return EXIT_PC_STALE;
+ case 251:
+ /* ALARM */
+ gen_helper_set_alarm(tmp);
+ break;
+
default:
/* The basic registers are data only, and unknown registers
are read-zero, write-ignore. */
--
1.7.4.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH 6/6] target-alpha: Add high-resolution access to wall clock and an alarm.
2011-08-25 21:45 ` [Qemu-devel] [PATCH 6/6] target-alpha: Add high-resolution access to wall clock and an alarm Richard Henderson
@ 2011-08-26 3:51 ` Peter Maydell
2011-08-26 9:07 ` Paolo Bonzini
0 siblings, 1 reply; 17+ messages in thread
From: Peter Maydell @ 2011-08-26 3:51 UTC (permalink / raw)
To: Richard Henderson; +Cc: Paolo Bonzini, qemu-devel
On 25 August 2011 22:45, Richard Henderson <rth@twiddle.net> wrote:
> @@ -1604,6 +1607,12 @@ static void gen_mfpr(int ra, int regno)
> return;
> }
>
> + if (regno == 250) {
> + /* WALL_TIME */
> + gen_helper_get_time(cpu_ir[ra]);
> + return;
> + }
> +
> /* The basic registers are data only, and unknown registers
> are read-zero, write-ignore. */
> if (data == 0) {
> @@ -1650,6 +1659,11 @@ static ExitStatus gen_mtpr(DisasContext *ctx, int rb, int regno)
> gen_helper_halt(tmp);
> return EXIT_PC_STALE;
>
> + case 251:
> + /* ALARM */
> + gen_helper_set_alarm(tmp);
> + break;
> +
> default:
> /* The basic registers are data only, and unknown registers
> are read-zero, write-ignore. */
Don't you need some magic around helper calls that read/write
the time to keep -icount working? I don't understand this but
Paolo does...
-- PMM
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH 6/6] target-alpha: Add high-resolution access to wall clock and an alarm.
2011-08-26 3:51 ` Peter Maydell
@ 2011-08-26 9:07 ` Paolo Bonzini
2011-08-26 16:28 ` Richard Henderson
0 siblings, 1 reply; 17+ messages in thread
From: Paolo Bonzini @ 2011-08-26 9:07 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, Richard Henderson
On 08/26/2011 05:51 AM, Peter Maydell wrote:
> Don't you need some magic around helper calls that read/write
> the time to keep -icount working? I don't understand this but
> Paolo does...
Let's say I understand the theory (how icount relies on it) more than
the practice (how the targets should do it). :)
Paolo
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH 6/6] target-alpha: Add high-resolution access to wall clock and an alarm.
2011-08-26 9:07 ` Paolo Bonzini
@ 2011-08-26 16:28 ` Richard Henderson
2011-08-26 16:36 ` Peter Maydell
0 siblings, 1 reply; 17+ messages in thread
From: Richard Henderson @ 2011-08-26 16:28 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: Peter Maydell, qemu-devel
On 08/25/2011 11:07 PM, Paolo Bonzini wrote:
> On 08/26/2011 05:51 AM, Peter Maydell wrote:
>> Don't you need some magic around helper calls that read/write
>> the time to keep -icount working? I don't understand this but
>> Paolo does...
>
> Let's say I understand the theory (how icount relies on it) more than the practice (how the targets should do it). :)
Heh. Well, let's say that while I've aped the other targets in
how icount is treated in the translator, I have no idea what it
is really supposed to accomplish, and so have never used it.
r~
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH 6/6] target-alpha: Add high-resolution access to wall clock and an alarm.
2011-08-26 16:28 ` Richard Henderson
@ 2011-08-26 16:36 ` Peter Maydell
2011-08-26 20:03 ` Richard Henderson
` (2 more replies)
0 siblings, 3 replies; 17+ messages in thread
From: Peter Maydell @ 2011-08-26 16:36 UTC (permalink / raw)
To: Richard Henderson; +Cc: Paolo Bonzini, qemu-devel
On 26 August 2011 17:28, Richard Henderson <rth@twiddle.net> wrote:
> On 08/25/2011 11:07 PM, Paolo Bonzini wrote:
>> On 08/26/2011 05:51 AM, Peter Maydell wrote:
>>> Don't you need some magic around helper calls that read/write
>>> the time to keep -icount working? I don't understand this but
>>> Paolo does...
>>
>> Let's say I understand the theory (how icount relies on it)
>> more than the practice (how the targets should do it). :)
>
> Heh. Well, let's say that while I've aped the other targets in
> how icount is treated in the translator, I have no idea what it
> is really supposed to accomplish, and so have never used it.
Well, "what it's supposed to accomplish" is straightforward
enough, we want to keep a count of cycles executed (and I think
also maintain determinism, although that I'm less certain about).
Since we only update the count at the start of each basic block,
we (potentially) have to stop the basic block where we hit an
I/O operation which fiddles with the timer. For I/O via memory
accesses this is all dealt with by the generic code, but where
the CPU has some instruction which does things with timers not
via a memory access there needs to be a bit of special casing.
Look at the way target-i386 and target-mips use gen_io_start()
and gen_io_end() around x86 io insns and MIPS mtc0. I think
that what you need is (a) to bracket with gen_io_start/end
and (b) to end the translation block, but that's really just
guesswork from the existing code...
-- PMM
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH 6/6] target-alpha: Add high-resolution access to wall clock and an alarm.
2011-08-26 16:36 ` Peter Maydell
@ 2011-08-26 20:03 ` Richard Henderson
2011-08-26 20:12 ` Richard Henderson
2011-08-27 16:44 ` Edgar E. Iglesias
2 siblings, 0 replies; 17+ messages in thread
From: Richard Henderson @ 2011-08-26 20:03 UTC (permalink / raw)
To: Peter Maydell; +Cc: Paolo Bonzini, qemu-devel
On 08/26/2011 06:36 AM, Peter Maydell wrote:
> Look at the way target-i386 and target-mips use gen_io_start()
> and gen_io_end() around x86 io insns and MIPS mtc0. I think
> that what you need is (a) to bracket with gen_io_start/end
> and (b) to end the translation block, but that's really just
> guesswork from the existing code...
I'll be applying this on top of 6/6. Look sane?
r~
---
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 37f2f20..8f0dc3e 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -1609,7 +1609,17 @@ static void gen_mfpr(int ra, int regno)
if (regno == 250) {
/* WALL_TIME */
- gen_helper_get_time(cpu_ir[ra]);
+ if (use_iocount) {
+ /* Mark as an IO operation because we read the time. */
+ gen_io_start();
+ gen_helper_get_time(cpu_ir[ra]);
+ gen_io_end();
+ /* Other targets break the TB to be able to take timer
+ interrupts immediately. This doesn't apply to Alpha
+ because we never take interrupts in PALmode. */
+ } else {
+ gen_helper_get_time(cpu_ir[ra]);
+ }
return;
}
@@ -1661,7 +1671,14 @@ static ExitStatus gen_mtpr(DisasContext *ctx, int rb, int regno)
case 251:
/* ALARM */
- gen_helper_set_alarm(tmp);
+ if (use_icount) {
+ /* Mark as an IO operation because we reference the time. */
+ gen_io_start();
+ gen_helper_set_alarm(tmp);
+ gen_io_end();
+ } else {
+ gen_helper_set_alarm(tmp);
+ }
break;
default:
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH 6/6] target-alpha: Add high-resolution access to wall clock and an alarm.
2011-08-26 16:36 ` Peter Maydell
2011-08-26 20:03 ` Richard Henderson
@ 2011-08-26 20:12 ` Richard Henderson
2011-08-27 16:44 ` Edgar E. Iglesias
2 siblings, 0 replies; 17+ messages in thread
From: Richard Henderson @ 2011-08-26 20:12 UTC (permalink / raw)
To: Peter Maydell; +Cc: Paolo Bonzini, qemu-devel
On 08/26/2011 06:36 AM, Peter Maydell wrote:
> Look at the way target-i386 and target-mips use gen_io_start()
> and gen_io_end() around x86 io insns and MIPS mtc0. I think
> that what you need is (a) to bracket with gen_io_start/end
> and (b) to end the translation block, but that's really just
> guesswork from the existing code...
Hmph. I suspect that the alpha port has never worked with
icount. Trying to boot a kernel with it results in millions
of "Bad clock read" messages.
I'm 20 minutes from leaving for holidays. I'll put this on
the to-do list for when I get back.
r~
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH 6/6] target-alpha: Add high-resolution access to wall clock and an alarm.
2011-08-26 16:36 ` Peter Maydell
2011-08-26 20:03 ` Richard Henderson
2011-08-26 20:12 ` Richard Henderson
@ 2011-08-27 16:44 ` Edgar E. Iglesias
2 siblings, 0 replies; 17+ messages in thread
From: Edgar E. Iglesias @ 2011-08-27 16:44 UTC (permalink / raw)
To: Peter Maydell; +Cc: Paolo Bonzini, qemu-devel, Richard Henderson
On Fri, Aug 26, 2011 at 05:36:19PM +0100, Peter Maydell wrote:
> On 26 August 2011 17:28, Richard Henderson <rth@twiddle.net> wrote:
> > On 08/25/2011 11:07 PM, Paolo Bonzini wrote:
> >> On 08/26/2011 05:51 AM, Peter Maydell wrote:
> >>> Don't you need some magic around helper calls that read/write
> >>> the time to keep -icount working? I don't understand this but
> >>> Paolo does...
> >>
> >> Let's say I understand the theory (how icount relies on it)
> >> more than the practice (how the targets should do it). :)
> >
> > Heh. Well, let's say that while I've aped the other targets in
> > how icount is treated in the translator, I have no idea what it
> > is really supposed to accomplish, and so have never used it.
>
> Well, "what it's supposed to accomplish" is straightforward
> enough, we want to keep a count of cycles executed (and I think
> also maintain determinism, although that I'm less certain about).
> Since we only update the count at the start of each basic block,
> we (potentially) have to stop the basic block where we hit an
> I/O operation which fiddles with the timer. For I/O via memory
> accesses this is all dealt with by the generic code, but where
> the CPU has some instruction which does things with timers not
> via a memory access there needs to be a bit of special casing.
>
> Look at the way target-i386 and target-mips use gen_io_start()
> and gen_io_end() around x86 io insns and MIPS mtc0. I think
> that what you need is (a) to bracket with gen_io_start/end
> and (b) to end the translation block, but that's really just
> guesswork from the existing code...
I think thats right, you need both.
If you forget the gen_io_start/end calls, you'll notice. Everytime
the timer is read you'll hit the "Bad clock read" from cpus.c.
IIUC, If you dont end the TB after timer reads, the read will return
a time in the future (i.e the insns beyond the read will be accounted
as already executed at the point where you read the time).
For alarm setups, you need to end the TB to get precise deliveries, otherwise
I think you risk executing insns beyond the point when the timer should
have fired. Maybe not so likely unless you're setting timers to very
short intervals though.
Cheers
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PULL][PATCH 0/6] Alpha system emulation, v9
2011-08-25 21:45 [Qemu-devel] [PULL][PATCH 0/6] Alpha system emulation, v9 Richard Henderson
` (5 preceding siblings ...)
2011-08-25 21:45 ` [Qemu-devel] [PATCH 6/6] target-alpha: Add high-resolution access to wall clock and an alarm Richard Henderson
@ 2011-08-25 21:59 ` Richard Henderson
6 siblings, 0 replies; 17+ messages in thread
From: Richard Henderson @ 2011-08-25 21:59 UTC (permalink / raw)
To: qemu-devel
On 08/25/2011 11:45 AM, Richard Henderson wrote:
> Changes v8->v9
> * Updates for memory api.
>
> Please pull from
>
> git://repo.or.cz/qemu/rth.git axp-system-7
>
>
> r~
>
>
> Richard Henderson (6):
> target-alpha: Add custom PALcode image for CLIPPER emulation.
> target-alpha: Add CLIPPER emulation.
> target-alpha: Add CLIPPER emulation.
> target-alpha: Implement WAIT IPR.
> target-alpha: Implement HALT IPR.
> target-alpha: Add high-resolution access to wall clock and an alarm.
I must have done something silly in between git-format-patch and
git-send-email; clearly patches 2 and 3 shouldn't be duplicates.
The git branch is correct, however.
r~
^ permalink raw reply [flat|nested] 17+ messages in thread