From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:36879) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R0j1Q-0003TI-ED for qemu-devel@nongnu.org; Mon, 05 Sep 2011 19:56:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R0j1H-0003JT-Up for qemu-devel@nongnu.org; Mon, 05 Sep 2011 19:56:06 -0400 Received: from [188.134.19.124] (port=53323 helo=octofox.metropolis) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R0j1G-0003IX-BT for qemu-devel@nongnu.org; Mon, 05 Sep 2011 19:56:03 -0400 From: Max Filippov Date: Tue, 6 Sep 2011 03:55:39 +0400 Message-Id: <1315266957-22979-16-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1315266957-22979-1-git-send-email-jcmvbkbc@gmail.com> References: <1315266957-22979-1-git-send-email-jcmvbkbc@gmail.com> Subject: [Qemu-devel] [PATCH v5 15/33] target-xtensa: implement CACHE group List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: jcmvbkbc@gmail.com All operations in this group are no-ops, because cache ought to be transparent to applications. However cache may be abused, then we'll need to actually implement these opcodes. Signed-off-by: Max Filippov --- target-xtensa/translate.c | 95 ++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 94 insertions(+), 1 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 4f1c18e..7d383b3 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1012,7 +1012,100 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 7: /*CACHEc*/ - TBD(); + if (RRI8_T < 8) { + HAS_OPTION(XTENSA_OPTION_DCACHE); + } + + switch (RRI8_T) { + case 0: /*DPFRc*/ + break; + + case 1: /*DPFWc*/ + break; + + case 2: /*DPFROc*/ + break; + + case 3: /*DPFWOc*/ + break; + + case 4: /*DHWBc*/ + break; + + case 5: /*DHWBIc*/ + break; + + case 6: /*DHIc*/ + break; + + case 7: /*DIIc*/ + break; + + case 8: /*DCEc*/ + switch (OP1) { + case 0: /*DPFLl*/ + HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); + break; + + case 2: /*DHUl*/ + HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); + break; + + case 3: /*DIUl*/ + HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); + break; + + case 4: /*DIWBc*/ + HAS_OPTION(XTENSA_OPTION_DCACHE); + break; + + case 5: /*DIWBIc*/ + HAS_OPTION(XTENSA_OPTION_DCACHE); + break; + + default: /*reserved*/ + RESERVED(); + break; + + } + break; + + case 12: /*IPFc*/ + HAS_OPTION(XTENSA_OPTION_ICACHE); + break; + + case 13: /*ICEc*/ + switch (OP1) { + case 0: /*IPFLl*/ + HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); + break; + + case 2: /*IHUl*/ + HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); + break; + + case 3: /*IIUl*/ + HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); + break; + + default: /*reserved*/ + RESERVED(); + break; + } + break; + + case 14: /*IHIc*/ + HAS_OPTION(XTENSA_OPTION_ICACHE); + break; + + case 15: /*IIIc*/ + HAS_OPTION(XTENSA_OPTION_ICACHE); + break; + + default: /*reserved*/ + RESERVED(); + break; + } break; case 9: /*L16SI*/ -- 1.7.6