From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: jcmvbkbc@gmail.com
Subject: [Qemu-devel] [PATCH v5 26/33] target-xtensa: implement CPENABLE and PRID SRs
Date: Tue, 6 Sep 2011 03:55:50 +0400 [thread overview]
Message-ID: <1315266957-22979-27-git-send-email-jcmvbkbc@gmail.com> (raw)
In-Reply-To: <1315266957-22979-1-git-send-email-jcmvbkbc@gmail.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
hw/xtensa_sample.c | 1 +
target-xtensa/cpu.h | 2 ++
target-xtensa/translate.c | 7 +++++++
3 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/hw/xtensa_sample.c b/hw/xtensa_sample.c
index 0aeb7c8..31a6f70 100644
--- a/hw/xtensa_sample.c
+++ b/hw/xtensa_sample.c
@@ -55,6 +55,7 @@ static void xtensa_init(ram_addr_t ram_size,
exit(1);
}
qemu_register_reset(xtensa_sample_reset, env);
+ env->sregs[PRID] = n;
}
ram = g_malloc(sizeof(*ram));
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 474466c..37f8b7f 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -118,12 +118,14 @@ enum {
DEPC = 192,
EPS2 = 194,
EXCSAVE1 = 209,
+ CPENABLE = 224,
INTSET = 226,
INTCLEAR = 227,
INTENABLE = 228,
PS = 230,
EXCCAUSE = 232,
CCOUNT = 234,
+ PRID = 235,
EXCVADDR = 238,
CCOMPARE = 240,
};
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index cee1f1c..d08b0ca 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -101,12 +101,14 @@ static const char * const sregnames[256] = {
[EXCSAVE1 + 4] = "EXCSAVE5",
[EXCSAVE1 + 5] = "EXCSAVE6",
[EXCSAVE1 + 6] = "EXCSAVE7",
+ [CPENABLE] = "CPENABLE",
[INTSET] = "INTSET",
[INTCLEAR] = "INTCLEAR",
[INTENABLE] = "INTENABLE",
[PS] = "PS",
[EXCCAUSE] = "EXCCAUSE",
[CCOUNT] = "CCOUNT",
+ [PRID] = "PRID",
[EXCVADDR] = "EXCVADDR",
[CCOMPARE] = "CCOMPARE0",
[CCOMPARE + 1] = "CCOMPARE1",
@@ -476,6 +478,10 @@ static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
gen_jumpi_check_loop_end(dc, -1);
}
+static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+{
+}
+
static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
uint32_t id = sr - CCOMPARE;
@@ -502,6 +508,7 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
[INTCLEAR] = gen_wsr_intclear,
[INTENABLE] = gen_wsr_intenable,
[PS] = gen_wsr_ps,
+ [PRID] = gen_wsr_prid,
[CCOMPARE] = gen_wsr_ccompare,
[CCOMPARE + 1] = gen_wsr_ccompare,
[CCOMPARE + 2] = gen_wsr_ccompare,
--
1.7.6
next prev parent reply other threads:[~2011-09-05 23:56 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-05 23:55 [Qemu-devel] [PATCH v5 00/32] target-xtensa: new target architecture Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 01/33] target-xtensa: add target stubs Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 02/33] target-xtensa: add target to the configure script Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 03/33] target-xtensa: implement disas_xtensa_insn Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 04/33] target-xtensa: implement narrow instructions Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 05/33] target-xtensa: implement RT0 group Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 06/33] target-xtensa: add sample board Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 07/33] target-xtensa: implement conditional jumps Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 08/33] target-xtensa: implement JX/RET0/CALLX Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 09/33] target-xtensa: add special and user registers Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 10/33] target-xtensa: implement RST3 group Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 11/33] target-xtensa: implement shifts (ST1 and RST1 groups) Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 12/33] target-xtensa: implement LSAI group Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 13/33] target-xtensa: mark reserved and TBD opcodes Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 14/33] target-xtensa: implement SYNC group Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 15/33] target-xtensa: implement CACHE group Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 16/33] target-xtensa: add PS register and access control Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 17/33] target-xtensa: implement exceptions Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 18/33] target-xtensa: implement RST2 group (32 bit mul/div/rem) Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 19/33] target-xtensa: implement windowed registers Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 20/33] target-xtensa: implement loop option Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 21/33] target-xtensa: implement extended L32R Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 22/33] target-xtensa: implement unaligned exception option Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 23/33] target-xtensa: implement SIMCALL Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 24/33] target-xtensa: implement interrupt option Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 25/33] target-xtensa: implement accurate window check Max Filippov
2011-09-05 23:55 ` Max Filippov [this message]
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 27/33] target-xtensa: implement relocatable vectors Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 28/33] target-xtensa: add gdb support Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 29/33] target-xtensa: implement memory protection options Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 30/33] target-xtensa: implement boolean option Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 31/33] target-xtensa: add dc232b core and board Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 32/33] MAINTAINERS: add xtensa maintainer Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 33/33] target-xtensa: add regression testsuite Max Filippov
2011-09-10 18:36 ` [Qemu-devel] [PATCH v5 00/32] target-xtensa: new target architecture Blue Swirl
2011-09-10 20:55 ` Stefan Weil
2011-09-11 18:06 ` Max Filippov
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