From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: jcmvbkbc@gmail.com
Subject: [Qemu-devel] [PATCH v5 30/33] target-xtensa: implement boolean option
Date: Tue, 6 Sep 2011 03:55:54 +0400 [thread overview]
Message-ID: <1315266957-22979-31-git-send-email-jcmvbkbc@gmail.com> (raw)
In-Reply-To: <1315266957-22979-1-git-send-email-jcmvbkbc@gmail.com>
See ISA, 4.3.9
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
target-xtensa/cpu.h | 1 +
target-xtensa/translate.c | 109 +++++++++++++++++++++++++++++++++++----------
2 files changed, 86 insertions(+), 24 deletions(-)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 14d62fa..339075d 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -110,6 +110,7 @@ enum {
LEND = 1,
LCOUNT = 2,
SAR = 3,
+ BR = 4,
LITBASE = 5,
SCOMPARE1 = 12,
WINDOW_BASE = 72,
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 20a6834..93a807e 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -76,6 +76,7 @@ static const char * const sregnames[256] = {
[LEND] = "LEND",
[LCOUNT] = "LCOUNT",
[SAR] = "SAR",
+ [BR] = "BR",
[LITBASE] = "LITBASE",
[SCOMPARE1] = "SCOMPARE1",
[WINDOW_BASE] = "WINDOW_BASE",
@@ -434,6 +435,11 @@ static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
dc->sar_m32_5bit = false;
}
+static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
+{
+ tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
+}
+
static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
{
tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
@@ -536,6 +542,7 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
[LBEG] = gen_wsr_lbeg,
[LEND] = gen_wsr_lend,
[SAR] = gen_wsr_sar,
+ [BR] = gen_wsr_br,
[LITBASE] = gen_wsr_litbase,
[WINDOW_BASE] = gen_wsr_windowbase,
[WINDOW_START] = gen_wsr_windowstart,
@@ -974,23 +981,28 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 8: /*ANY4p*/
- HAS_OPTION(XTENSA_OPTION_BOOLEAN);
- TBD();
- break;
-
case 9: /*ALL4p*/
- HAS_OPTION(XTENSA_OPTION_BOOLEAN);
- TBD();
- break;
-
case 10: /*ANY8p*/
- HAS_OPTION(XTENSA_OPTION_BOOLEAN);
- TBD();
- break;
-
case 11: /*ALL8p*/
HAS_OPTION(XTENSA_OPTION_BOOLEAN);
- TBD();
+ {
+ const unsigned shift = (RRR_R & 2) ? 8 : 4;
+ TCGv_i32 mask = tcg_const_i32(
+ ((1 << shift) - 1) << RRR_S);
+ TCGv_i32 tmp = tcg_temp_new_i32();
+
+ tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
+ if (RRR_R & 1) { /*ALL*/
+ tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
+ } else { /*ANY*/
+ tcg_gen_add_i32(tmp, tmp, mask);
+ }
+ tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
+ tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
+ tmp, RRR_T, 1);
+ tcg_temp_free(mask);
+ tcg_temp_free(tmp);
+ }
break;
default: /*reserved*/
@@ -1339,7 +1351,9 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 2: /*RST2*/
- gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
+ if (OP2 >= 8) {
+ gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
+ }
if (OP2 >= 12) {
HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
@@ -1350,6 +1364,42 @@ static void disas_xtensa_insn(DisasContext *dc)
}
switch (OP2) {
+#define BOOLEAN_LOGIC(fn, r, s, t) \
+ do { \
+ HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
+ TCGv_i32 tmp1 = tcg_temp_new_i32(); \
+ TCGv_i32 tmp2 = tcg_temp_new_i32(); \
+ \
+ tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
+ tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
+ tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
+ tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
+ tcg_temp_free(tmp1); \
+ tcg_temp_free(tmp2); \
+ } while (0)
+
+ case 0: /*ANDBp*/
+ BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
+ break;
+
+ case 1: /*ANDBCp*/
+ BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
+ break;
+
+ case 2: /*ORBp*/
+ BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
+ break;
+
+ case 3: /*ORBCp*/
+ BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
+ break;
+
+ case 4: /*XORBp*/
+ BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
+ break;
+
+#undef BOOLEAN_LOGIC
+
case 8: /*MULLi*/
HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
@@ -1536,13 +1586,21 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 12: /*MOVFp*/
- HAS_OPTION(XTENSA_OPTION_BOOLEAN);
- TBD();
- break;
-
case 13: /*MOVTp*/
HAS_OPTION(XTENSA_OPTION_BOOLEAN);
- TBD();
+ gen_window_check2(dc, RRR_R, RRR_S);
+ {
+ int label = gen_new_label();
+ TCGv_i32 tmp = tcg_temp_new_i32();
+
+ tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
+ tcg_gen_brcondi_i32(
+ OP2 & 1 ? TCG_COND_EQ : TCG_COND_NE,
+ tmp, 0, label);
+ tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
+ gen_set_label(label);
+ tcg_temp_free(tmp);
+ }
break;
case 14: /*RUR*/
@@ -1954,13 +2012,16 @@ static void disas_xtensa_insn(DisasContext *dc)
case 1: /*B1*/
switch (BRI8_R) {
case 0: /*BFp*/
- HAS_OPTION(XTENSA_OPTION_BOOLEAN);
- TBD();
- break;
-
case 1: /*BTp*/
HAS_OPTION(XTENSA_OPTION_BOOLEAN);
- TBD();
+ {
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
+ gen_brcondi(dc,
+ BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
+ tmp, 0, 4 + RRI8_IMM8_SE);
+ tcg_temp_free(tmp);
+ }
break;
case 8: /*LOOP*/
--
1.7.6
next prev parent reply other threads:[~2011-09-05 23:56 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-05 23:55 [Qemu-devel] [PATCH v5 00/32] target-xtensa: new target architecture Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 01/33] target-xtensa: add target stubs Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 02/33] target-xtensa: add target to the configure script Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 03/33] target-xtensa: implement disas_xtensa_insn Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 04/33] target-xtensa: implement narrow instructions Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 05/33] target-xtensa: implement RT0 group Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 06/33] target-xtensa: add sample board Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 07/33] target-xtensa: implement conditional jumps Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 08/33] target-xtensa: implement JX/RET0/CALLX Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 09/33] target-xtensa: add special and user registers Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 10/33] target-xtensa: implement RST3 group Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 11/33] target-xtensa: implement shifts (ST1 and RST1 groups) Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 12/33] target-xtensa: implement LSAI group Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 13/33] target-xtensa: mark reserved and TBD opcodes Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 14/33] target-xtensa: implement SYNC group Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 15/33] target-xtensa: implement CACHE group Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 16/33] target-xtensa: add PS register and access control Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 17/33] target-xtensa: implement exceptions Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 18/33] target-xtensa: implement RST2 group (32 bit mul/div/rem) Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 19/33] target-xtensa: implement windowed registers Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 20/33] target-xtensa: implement loop option Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 21/33] target-xtensa: implement extended L32R Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 22/33] target-xtensa: implement unaligned exception option Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 23/33] target-xtensa: implement SIMCALL Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 24/33] target-xtensa: implement interrupt option Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 25/33] target-xtensa: implement accurate window check Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 26/33] target-xtensa: implement CPENABLE and PRID SRs Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 27/33] target-xtensa: implement relocatable vectors Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 28/33] target-xtensa: add gdb support Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 29/33] target-xtensa: implement memory protection options Max Filippov
2011-09-05 23:55 ` Max Filippov [this message]
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 31/33] target-xtensa: add dc232b core and board Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 32/33] MAINTAINERS: add xtensa maintainer Max Filippov
2011-09-05 23:55 ` [Qemu-devel] [PATCH v5 33/33] target-xtensa: add regression testsuite Max Filippov
2011-09-10 18:36 ` [Qemu-devel] [PATCH v5 00/32] target-xtensa: new target architecture Blue Swirl
2011-09-10 20:55 ` Stefan Weil
2011-09-11 18:06 ` Max Filippov
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