[Qemu-devel] [PATCH] mips_malta: move i8259 initialization after piix4 initialization

[Avi Kivity <avi@redhat.com>]

i8259 is an ISA device (or at least, depends on the ISA infrastructure to
register its ioport); and the ISA bus is supplied by piix4.  Later patches
make this dependency explicit.

Move the i8259 initialization until after the ISA bus is created; and supply
a new qemu_irq to PCI initialization, since the i8259 isn't ready yet.  Later
wire the new qemu_irq to the i8259.

Signed-off-by: Avi Kivity <avi@redhat.com>
---

Part of batch 7, but nasty, so sending it by itself.

Not sure this is the right approach - the i8259 is not really an ISA device.
However, disentangling it from ISA is hard.

 hw/mips_malta.c |   27 ++++++++++++++++++++++-----
 1 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 0110daa..f7297e7 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -72,6 +72,10 @@
     SerialState *uart;
 } MaltaFPGAState;
 
+typedef struct MaltaISAState {
+    qemu_irq *i8259;
+} MaltaISAState;
+
 static ISADevice *pit;
 
 static struct _loaderparams {
@@ -763,6 +767,15 @@ static void cpu_request_exit(void *opaque, int irq, int level)
     }
 }
 
+static void malta_isa_irq_handler(void *opaque, int n, int level)
+{
+    MaltaISAState *s = opaque;
+
+    if (s->i8259) {
+        qemu_set_irq(s->i8259[n], level);
+    }
+}
+
 static
 void mips_malta_init (ram_addr_t ram_size,
                       const char *boot_device,
@@ -778,7 +791,8 @@ void mips_malta_init (ram_addr_t ram_size,
     int64_t kernel_entry;
     PCIBus *pci_bus;
     CPUState *env;
-    qemu_irq *i8259;
+    qemu_irq *i8259, *isa_irq;
+    MaltaISAState *malta_isa = g_new0(MaltaISAState, 1);
     qemu_irq *cpu_exit_irq;
     int piix4_devfn;
     i2c_bus *smbus;
@@ -928,17 +942,20 @@ void mips_malta_init (ram_addr_t ram_size,
     cpu_mips_irq_init_cpu(env);
     cpu_mips_clock_init(env);
 
-    /* Interrupt controller */
-    /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
-    i8259 = i8259_init(env->irq[2]);
+    isa_irq = qemu_allocate_irqs(malta_isa_irq_handler, malta_isa, 16);
 
     /* Northbridge */
-    pci_bus = gt64120_register(i8259);
+    pci_bus = gt64120_register(isa_irq);
 
     /* Southbridge */
     ide_drive_get(hd, MAX_IDE_BUS);
 
     piix4_devfn = piix4_init(pci_bus, 80);
+
+    /* Interrupt controller */
+    /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
+    malta_isa->i8259 = i8259 = i8259_init(env->irq[2]);
+
     isa_bus_irqs(i8259);
     pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
     usb_uhci_piix4_init(pci_bus, piix4_devfn + 2);
-- 
1.7.6.1