From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:42257) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R3l3L-0007F0-Mc for qemu-devel@nongnu.org; Wed, 14 Sep 2011 04:42:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R3l3E-0000Tv-O1 for qemu-devel@nongnu.org; Wed, 14 Sep 2011 04:42:43 -0400 From: Alexander Graf Date: Wed, 14 Sep 2011 10:42:30 +0200 Message-Id: <1315989802-18753-7-git-send-email-agraf@suse.de> In-Reply-To: <1315989802-18753-1-git-send-email-agraf@suse.de> References: <1315989802-18753-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH 06/58] PPC: Extend MPIC MMIO range List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel Developers Cc: Blue Swirl , qemu-ppc@nongnu.org, Aurelien Jarno The MPIC exports a page for each CPU that it controls. To support more than one CPU, we need to also reserve the MMIO space according to the amount of CPUs we want to support. Signed-off-by: Alexander Graf --- hw/openpic.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index cf89f23..f7d5583 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -128,7 +128,7 @@ enum { #define MPIC_MSI_REG_START 0x11C00 #define MPIC_MSI_REG_SIZE 0x100 #define MPIC_CPU_REG_START 0x20000 -#define MPIC_CPU_REG_SIZE 0x100 +#define MPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) enum mpic_ide_bits { IDR_EP = 0, -- 1.6.0.2