From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:40207) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R6lFe-0004ei-TI for qemu-devel@nongnu.org; Thu, 22 Sep 2011 11:32:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R6lFZ-0006TF-3a for qemu-devel@nongnu.org; Thu, 22 Sep 2011 11:31:50 -0400 Received: from mail-ww0-f53.google.com ([74.125.82.53]:54880) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R6lFY-0006RZ-Uk for qemu-devel@nongnu.org; Thu, 22 Sep 2011 11:31:45 -0400 Received: by mail-ww0-f53.google.com with SMTP id 14so2052898wwg.10 for ; Thu, 22 Sep 2011 08:31:44 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 22 Sep 2011 08:30:47 -0700 Message-Id: <1316705449-17187-5-git-send-email-rth@twiddle.net> In-Reply-To: <1316705449-17187-1-git-send-email-rth@twiddle.net> References: <1316705449-17187-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 4/6] target-alpha: Implement WAIT IPR. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Richard Henderson --- target-alpha/translate.c | 31 +++++++++++++++++++++---------- 1 files changed, 21 insertions(+), 10 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index fb2e9e5..c1ef465 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1617,9 +1617,10 @@ static void gen_mfpr(int ra, int regno) } } -static void gen_mtpr(int rb, int regno) +static ExitStatus gen_mtpr(DisasContext *ctx, int rb, int regno) { TCGv tmp; + int data; if (rb == 31) { tmp = tcg_const_i64(0); @@ -1627,19 +1628,27 @@ static void gen_mtpr(int rb, int regno) tmp = cpu_ir[rb]; } - /* These two register numbers perform a TLB cache flush. Thankfully we - can only do this inside PALmode, which means that the current basic - block cannot be affected by the change in mappings. */ - if (regno == 255) { + switch (regno) { + case 255: /* TBIA */ gen_helper_tbia(); - } else if (regno == 254) { + break; + + case 254: /* TBIS */ gen_helper_tbis(tmp); - } else { + break; + + case 253: + /* WAIT */ + tmp = tcg_const_i64(1); + tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUState, halted)); + return gen_excp(ctx, EXCP_HLT, 0); + + default: /* The basic registers are data only, and unknown registers are read-zero, write-ignore. */ - int data = cpu_pr_data(regno); + data = cpu_pr_data(regno); if (data != 0) { if (data & PR_BYTE) { tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE); @@ -1649,11 +1658,14 @@ static void gen_mtpr(int rb, int regno) tcg_gen_st_i64(tmp, cpu_env, data); } } + break; } if (rb == 31) { tcg_temp_free(tmp); } + + return NO_EXIT; } #endif /* !USER_ONLY*/ @@ -3061,8 +3073,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) /* HW_MTPR (PALcode) */ #ifndef CONFIG_USER_ONLY if (ctx->tb->flags & TB_FLAGS_PAL_MODE) { - gen_mtpr(rb, insn & 0xffff); - break; + return gen_mtpr(ctx, rb, insn & 0xffff); } #endif goto invalid_opc; -- 1.7.6.2