[Qemu-devel] [PATCH 1/2] gt64xxx.c: fix length modifier in DPRINTF format string

[Qemu-devel] [PATCH 1/2] gt64xxx.c: fix length modifier in DPRINTF format string

[Antony Pavlov]

The commit fc2bf44972349b078d8310466c3866615500e67f
changed the type of val argument of the function gt64120_writel()
from uint32_t to uint64_t, so we need to change the corresponding
length modifier from '%x' to '%llx'.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 hw/gt64xxx.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index c7df8c4..0baa320 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -543,19 +543,19 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
         /* not really implemented */
         s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
         s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
-        DPRINTF("INTRCAUSE %x\n", val);
+        DPRINTF("INTRCAUSE %llx\n", val);
         break;
     case GT_INTRMASK:
         s->regs[saddr] = val & 0x3c3ffffe;
-        DPRINTF("INTRMASK %x\n", val);
+        DPRINTF("INTRMASK %llx\n", val);
         break;
     case GT_PCI0_ICMASK:
         s->regs[saddr] = val & 0x03fffffe;
-        DPRINTF("ICMASK %x\n", val);
+        DPRINTF("ICMASK %llx\n", val);
         break;
     case GT_PCI0_SERR0MASK:
         s->regs[saddr] = val & 0x0000003f;
-        DPRINTF("SERR0MASK %x\n", val);
+        DPRINTF("SERR0MASK %llx\n", val);
         break;
 
     /* Reserved when only PCI_0 is configured. */
-- 
1.7.5.4

Re: [Qemu-devel] [PATCH 1/2] gt64xxx.c: fix length modifier in DPRINTF format string

[Peter Maydell]

On 25 September 2011 19:14, Antony Pavlov <antonynpavlov@gmail.com> wrote:
> The commit fc2bf44972349b078d8310466c3866615500e67f
> changed the type of val argument of the function gt64120_writel()
> from uint32_t to uint64_t, so we need to change the corresponding
> length modifier from '%x' to '%llx'.

For a uint64_t you need to use PRIx64 -- '%llx' won't work on
systems where uint64_t isn't typedefed as 'long long'.

-- PMM

Re: [Qemu-devel] [PATCH 1/2] gt64xxx.c: fix length modifier in DPRINTF format string

[Antony Pavlov]

On 25 September 2011 23:22, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 25 September 2011 19:14, Antony Pavlov <antonynpavlov@gmail.com> wrote:
>> The commit fc2bf44972349b078d8310466c3866615500e67f
>> changed the type of val argument of the function gt64120_writel()
>> from uint32_t to uint64_t, so we need to change the corresponding
>> length modifier from '%x' to '%llx'.
>
> For a uint64_t you need to use PRIx64 -- '%llx' won't work on
> systems where uint64_t isn't typedefed as 'long long'.

Thanks! I will resend patches in a few seconds.

-- 
Best regards,
  Antony Pavlov

[Qemu-devel] [PATCH 1/2] gt64xxx.c: fix length modifier in DPRINTF format string

[Antony Pavlov]

The commit fc2bf44972349b078d8310466c3866615500e67f
changed the type of val argument of the function gt64120_writel()
from uint32_t to uint64_t, so we need to change the corresponding
length modifier from '%x' to '%llx'.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 hw/gt64xxx.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index c7df8c4..1defb6d 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -543,19 +543,19 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
         /* not really implemented */
         s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
         s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
-        DPRINTF("INTRCAUSE %x\n", val);
+        DPRINTF("INTRCAUSE %" PRIx64 "\n", val);
         break;
     case GT_INTRMASK:
         s->regs[saddr] = val & 0x3c3ffffe;
-        DPRINTF("INTRMASK %x\n", val);
+        DPRINTF("INTRMASK %" PRIx64 "\n", val);
         break;
     case GT_PCI0_ICMASK:
         s->regs[saddr] = val & 0x03fffffe;
-        DPRINTF("ICMASK %x\n", val);
+        DPRINTF("ICMASK %" PRIx64 "\n", val);
         break;
     case GT_PCI0_SERR0MASK:
         s->regs[saddr] = val & 0x0000003f;
-        DPRINTF("SERR0MASK %x\n", val);
+        DPRINTF("SERR0MASK %" PRIx64 "\n", val);
         break;
 
     /* Reserved when only PCI_0 is configured. */
-- 
1.7.5.4

Re: [Qemu-devel] [PATCH 1/2] gt64xxx.c: fix length modifier in DPRINTF format string

[Peter Maydell]

On 25 September 2011 21:02, Antony Pavlov <antonynpavlov@gmail.com> wrote:
> The commit fc2bf44972349b078d8310466c3866615500e67f
> changed the type of val argument of the function gt64120_writel()
> from uint32_t to uint64_t, so we need to change the corresponding
> length modifier from '%x' to '%llx'.

Revised patch looks OK but you forgot to update the commit message :-)


-- PMM

Re: [Qemu-devel] [PATCH 1/2] gt64xxx.c: fix length modifier in DPRINTF format string

[Antony Pavlov]

On 26 September 2011 00:56, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 25 September 2011 21:02, Antony Pavlov <antonynpavlov@gmail.com> wrote:
>> The commit fc2bf44972349b078d8310466c3866615500e67f
>> changed the type of val argument of the function gt64120_writel()
>> from uint32_t to uint64_t, so we need to change the corresponding
>> length modifier from '%x' to '%llx'.
>
> Revised patch looks OK but you forgot to update the commit message :-)

Aghhhh.

Next time I shell be more lucky. Wait for new patches.

-- 
Best regards,
  Antony Pavlov

[Qemu-devel] [PATCH 1/2] gt64xxx.c: fix length modifier in DPRINTF format string

[Antony Pavlov]

The commit fc2bf44972349b078d8310466c3866615500e67f
changed the type of val argument of the function gt64120_writel()
from uint32_t to uint64_t, so we need to change the corresponding
length modifier from "%x" to "%" PRIx64.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 hw/gt64xxx.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index c7df8c4..1defb6d 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -543,19 +543,19 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
         /* not really implemented */
         s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
         s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
-        DPRINTF("INTRCAUSE %x\n", val);
+        DPRINTF("INTRCAUSE %" PRIx64 "\n", val);
         break;
     case GT_INTRMASK:
         s->regs[saddr] = val & 0x3c3ffffe;
-        DPRINTF("INTRMASK %x\n", val);
+        DPRINTF("INTRMASK %" PRIx64 "\n", val);
         break;
     case GT_PCI0_ICMASK:
         s->regs[saddr] = val & 0x03fffffe;
-        DPRINTF("ICMASK %x\n", val);
+        DPRINTF("ICMASK %" PRIx64 "\n", val);
         break;
     case GT_PCI0_SERR0MASK:
         s->regs[saddr] = val & 0x0000003f;
-        DPRINTF("SERR0MASK %x\n", val);
+        DPRINTF("SERR0MASK %" PRIx64 "\n", val);
         break;
 
     /* Reserved when only PCI_0 is configured. */
-- 
1.7.5.4

[Qemu-devel] [PATCH 2/2] gt64xxx.c: remove reference to non-existing ISD_handle field

[Antony Pavlov]

The commit fc2bf44972349b078d8310466c3866615500e67f
removed ISD_handle field from struct GT64120State,
so remove the field from DPRINTF too.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 hw/gt64xxx.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index 1defb6d..35dc1cd 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -275,8 +275,9 @@ static void gt64120_isd_mapping(GT64120State *s)
     check_reserved_space(&start, &length);
     length = 0x1000;
     /* Map new address */
-    DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx" -> "TARGET_FMT_plx"@"TARGET_FMT_plx", %x\n", s->ISD_length, s->ISD_start,
-            length, start, s->ISD_handle);
+    DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx
+        " -> "TARGET_FMT_plx"@"TARGET_FMT_plx"\n",
+        s->ISD_length, s->ISD_start, length, start);
     s->ISD_start = start;
     s->ISD_length = length;
     memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
-- 
1.7.5.4

Re: [Qemu-devel] [Qemu-trivial] [PATCH 1/2] gt64xxx.c: fix length modifier in DPRINTF format string

[Stefan Hajnoczi]

On Mon, Sep 26, 2011 at 09:02:37AM +0400, Antony Pavlov wrote:
> The commit fc2bf44972349b078d8310466c3866615500e67f
> changed the type of val argument of the function gt64120_writel()
> from uint32_t to uint64_t, so we need to change the corresponding
> length modifier from "%x" to "%" PRIx64.
> 
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> ---
>  hw/gt64xxx.c |    8 ++++----
>  1 files changed, 4 insertions(+), 4 deletions(-)

When sending revised patches in the future, please include a version
number in the subject line like "[PATCH v2 1/2] ..." so that it is easy
to identify different revisions of the series.

Thanks, applied to the trivial patches tree:
http://repo.or.cz/w/qemu/stefanha.git/shortlog/refs/heads/trivial-patches

Stefan

Re: [Qemu-devel] [PATCH 1/2] gt64xxx.c: fix length modifier in DPRINTF format string

[Ray Wang]

Tested-by: Ray Wang <xianleiw@cn.ibm.com>

On 9/26/2011 1:02 PM, Antony Pavlov wrote:
> The commit fc2bf44972349b078d8310466c3866615500e67f
> changed the type of val argument of the function gt64120_writel()
> from uint32_t to uint64_t, so we need to change the corresponding
> length modifier from "%x" to "%" PRIx64.
>
> Signed-off-by: Antony Pavlov<antonynpavlov@gmail.com>
> ---
>   hw/gt64xxx.c |    8 ++++----
>   1 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
> index c7df8c4..1defb6d 100644
> --- a/hw/gt64xxx.c
> +++ b/hw/gt64xxx.c
> @@ -543,19 +543,19 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
>           /* not really implemented */
>           s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val&  0xfffffffe));
>           s->regs[saddr] |= !!(s->regs[saddr]&  0xfffffffe);
> -        DPRINTF("INTRCAUSE %x\n", val);
> +        DPRINTF("INTRCAUSE %" PRIx64 "\n", val);
>           break;
>       case GT_INTRMASK:
>           s->regs[saddr] = val&  0x3c3ffffe;
> -        DPRINTF("INTRMASK %x\n", val);
> +        DPRINTF("INTRMASK %" PRIx64 "\n", val);
>           break;
>       case GT_PCI0_ICMASK:
>           s->regs[saddr] = val&  0x03fffffe;
> -        DPRINTF("ICMASK %x\n", val);
> +        DPRINTF("ICMASK %" PRIx64 "\n", val);
>           break;
>       case GT_PCI0_SERR0MASK:
>           s->regs[saddr] = val&  0x0000003f;
> -        DPRINTF("SERR0MASK %x\n", val);
> +        DPRINTF("SERR0MASK %" PRIx64 "\n", val);
>           break;
>
>       /* Reserved when only PCI_0 is configured. */
It's good.

-- 
Best Regards,
-------------------------------------------------
Ray Wang
Linux Technology Center, KVM China
IBM Corp., Beijing, China
xianleiw@cn.ibm.com