[Qemu-devel] [PATCH 0/7] MIPS64 user mode emulation in QEMU with Cavium specific instruction support

[khansa@kics.edu.pk]

From: Khansa Butt <khansa@kics.edu.pk>

This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt
from HPCN Lab KICS UET Lahore.

This Patch series add support of MIPS64 user mode emulation in QEMU.
Along with we implemented Cavium specific instructions which We will use 
in SME (in sysem mode emulation of Octeon processor)

If you have any objection regarding the Implementation of
Cavium instructions please read following notes.

Notes
*****

The detail of some instructions are as follows
1)seq rd,rs,rt
seq-->rd = 1 if rs = rt
is equivalent to
xor rd,rs,rt
sltiu rd,rd,1
2)exts rt,rs,p,lenm1
rt = sign-extend(rs<p+lenm1:p>,lenm1)
>From reference manual of Cavium Networks
"Bit locations p + lenm1 to p are extracted from rs and the result is written into the
lowest bits of destination register rt. The remaining bits in rt are a sign-extension of
the most-significant bit of the bit field (i.e. rt<63:lenm1> are all duplicates of the
source-register bit rs<p+lenm1>)." so we can't use any of 8,16 or 32 bit
sign extention tcg function. To sign extend according to msb of bit field
we have our own implementation
3)dmul rd,rs,rt
This instruction is included in gen_arith() because it is three operand
double word multiply instruction.
-- 
1.7.3.4