From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:53281) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R91Ej-0001nT-QV for qemu-devel@nongnu.org; Wed, 28 Sep 2011 17:00:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R91Ei-0003xs-Iq for qemu-devel@nongnu.org; Wed, 28 Sep 2011 17:00:13 -0400 From: Benjamin Herrenschmidt In-Reply-To: <5B15DB32-18DF-4637-AD37-4BE652A031E3@suse.de> References: <4E832DE3.40503@siemens.com> <5B15DB32-18DF-4637-AD37-4BE652A031E3@suse.de> Content-Type: text/plain; charset="UTF-8" Date: Thu, 29 Sep 2011 06:58:44 +1000 Message-ID: <1317243524.29415.96.camel@pasglop> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] qemu-kvm: Role of flush_icache_range on PPC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Jan Kiszka , qemu-ppc@nongnu.org, qemu-devel Developers , kvm , David Gibson On Wed, 2011-09-28 at 16:26 +0200, Alexander Graf wrote: > > This makes sure that when device emulation overwrites code that is > already present in the cache of a CPU, it gets flushed from the > icache. I'm fairly sure we want that :). But let's ask Ben and David > as well. Hrm we don't need that. DMA doesn't flush the icache on power. The kernel will take care of it if necessary. The only case you do need it is when doing the initial load of the kernel or SLOF image before you execute it. Cheers, Ben.