From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:35708) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RARDQ-0007Aj-0T for qemu-devel@nongnu.org; Sun, 02 Oct 2011 14:56:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RARDO-0004Vb-2i for qemu-devel@nongnu.org; Sun, 02 Oct 2011 14:56:43 -0400 Received: from fmmailgate03.web.de ([217.72.192.234]:46448) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RARDN-0004VI-N2 for qemu-devel@nongnu.org; Sun, 02 Oct 2011 14:56:42 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 2 Oct 2011 20:56:48 +0200 Message-Id: <1317581808-9784-3-git-send-email-andreas.faerber@web.de> In-Reply-To: <1317581808-9784-1-git-send-email-andreas.faerber@web.de> References: <1317581808-9784-1-git-send-email-andreas.faerber@web.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: andreas.faerber@web.de Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [RFC 2/2] target-arm: Add support for Cortex-R4F List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , qemu-devel@nongnu.org All CPU-dependent initializations are currently done based on MIDR. Cortex-R4F shares the MIDR with Cortex-R4 though. Therefore consider the CPU model string, too (which is not cleared on reset). Cc: Peter Maydell Signed-off-by: Andreas F=C3=A4rber --- target-arm/helper.c | 35 +++++++++++++++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 21be805..2273492 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -196,6 +196,40 @@ static void cpu_reset_model_id(CPUARMState *env, uin= t32_t id) /* TODO other features */ set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_V7); + if (strcmp(env->cpu_model_str, "cortex-r4f") =3D=3D 0) { + uint8_t r =3D (id >> 20) & 0xf; + uint8_t p =3D id & 0xf; + uint8_t rev =3D 0; + set_feature(env, ARM_FEATURE_VFP); + set_feature(env, ARM_FEATURE_VFP3); + /* TODO VFPv3-D16 */ + /* Calculate FPSID value matching to MIDR */ + if (r =3D=3D 1) { + switch (p) { + case 0: + rev =3D 0x3; + break; + case 1: + rev =3D 0x4; + break; + case 2: + rev =3D 0x6; + break; + case 3: + rev =3D 0x7; + break; + case 4: + rev =3D 0x8; + break; + } + } + if (rev =3D=3D 0) { + cpu_abort(env, + "Cortex-R4F r%" PRIu8 "p%" PRIu8 " unsupported= ", + r, p); + } + env->vfp.xregs[ARM_VFP_FPSID] =3D 0x41023140 | (rev & 0xf); + } memcpy(env->cp15.c0_c1, cortexr4_cp15_c0_c1, 8 * sizeof(uint32_t= )); memcpy(env->cp15.c0_c2, cortexr4_cp15_c0_c2, 8 * sizeof(uint32_t= )); break; @@ -438,6 +472,7 @@ static const struct arm_cpu_t arm_cpu_names[] =3D { { ARM_CPUID_CORTEXA8, "cortex-a8"}, { ARM_CPUID_CORTEXA9, "cortex-a9"}, { ARM_CPUID_CORTEXR4_R1P4, "cortex-r4"}, + { ARM_CPUID_CORTEXR4_R1P4, "cortex-r4f"}, { ARM_CPUID_TI925T, "ti925t" }, { ARM_CPUID_PXA250, "pxa250" }, { ARM_CPUID_SA1100, "sa1100" }, --=20 1.7.3.4