From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:44055) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RBixV-0001if-C6 for qemu-devel@nongnu.org; Thu, 06 Oct 2011 04:05:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RBixO-0000rP-1h for qemu-devel@nongnu.org; Thu, 06 Oct 2011 04:05:36 -0400 From: Alexander Graf Date: Thu, 6 Oct 2011 10:05:11 +0200 Message-Id: <1317888366-10509-10-git-send-email-agraf@suse.de> In-Reply-To: <1317888366-10509-1-git-send-email-agraf@suse.de> References: <1317888366-10509-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH 09/64] PPC: MPIC: Remove read functionality for WO registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , qemu-ppc@nongnu.org The IPI dispatch registers are write only according to every MPIC spec I have found. So instead of pretending you could read back something from them, better not handle them at all. Reported-by: Elie Richa Signed-off-by: Alexander Graf --- hw/openpic.c | 7 ------- 1 files changed, 0 insertions(+), 7 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index 31ad175..dfec52e 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -952,13 +952,6 @@ static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr, case 0xB0: /* PEOI */ retval = 0; break; -#if MAX_IPI > 0 - case 0x40: /* IDE */ - case 0x50: - idx = (addr - 0x40) >> 4; - retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE); - break; -#endif default: break; } -- 1.6.0.2