From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:44179) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RBixb-000221-Kr for qemu-devel@nongnu.org; Thu, 06 Oct 2011 04:06:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RBixO-0000ri-5p for qemu-devel@nongnu.org; Thu, 06 Oct 2011 04:05:43 -0400 From: Alexander Graf Date: Thu, 6 Oct 2011 10:05:12 +0200 Message-Id: <1317888366-10509-11-git-send-email-agraf@suse.de> In-Reply-To: <1317888366-10509-1-git-send-email-agraf@suse.de> References: <1317888366-10509-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH 10/64] PPC: MPIC: Fix CI bit definitions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , qemu-ppc@nongnu.org The bit definitions for critical interrupt routing are in PowerPC order (most significant bit is 0), while we end up shifting it with normal bit order. Turn the numbers around so we actually end up fetching the right ones. Signed-off-by: Alexander Graf --- hw/openpic.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index dfec52e..109c1bc 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -131,11 +131,11 @@ enum { #define MPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) enum mpic_ide_bits { - IDR_EP = 0, - IDR_CI0 = 1, - IDR_CI1 = 2, - IDR_P1 = 30, - IDR_P0 = 31, + IDR_EP = 31, + IDR_CI0 = 30, + IDR_CI1 = 29, + IDR_P1 = 1, + IDR_P0 = 0, }; #else -- 1.6.0.2