From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:44256) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RBixf-0002DG-6i for qemu-devel@nongnu.org; Thu, 06 Oct 2011 04:06:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RBixO-0000rn-67 for qemu-devel@nongnu.org; Thu, 06 Oct 2011 04:05:47 -0400 From: Alexander Graf Date: Thu, 6 Oct 2011 10:05:13 +0200 Message-Id: <1317888366-10509-12-git-send-email-agraf@suse.de> In-Reply-To: <1317888366-10509-1-git-send-email-agraf@suse.de> References: <1317888366-10509-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH 11/64] PPC: Bump MPIC up to 32 supported CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , qemu-ppc@nongnu.org The MPIC emulation is now capable of handling up to 32 CPUs. Reflect that in the code exporting the numbers out and fix an integer overflow while at it. Signed-off-by: Alexander Graf --- v1 -> v2: - Max cpus is 15 due to cINT routing - Report nb_cpus not MAX_CPUS in MPIC capabilities --- hw/openpic.c | 10 +++------- 1 files changed, 3 insertions(+), 7 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index 109c1bc..03e442b 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -63,7 +63,7 @@ #elif defined(USE_MPCxxx) -#define MAX_CPU 2 +#define MAX_CPU 15 #define MAX_IRQ 128 #define MAX_DBL 0 #define MAX_MBX 0 @@ -507,7 +507,7 @@ static inline void write_IRQreg (openpic_t *opp, int n_IRQ, break; case IRQ_IDE: tmp = val & 0xC0000000; - tmp |= val & ((1 << MAX_CPU) - 1); + tmp |= val & ((1ULL << MAX_CPU) - 1); opp->src[n_IRQ].ide = tmp; DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide); break; @@ -1283,7 +1283,7 @@ static void mpic_reset (void *opaque) mpp->glbc = 0x80000000; /* Initialise controller registers */ - mpp->frep = 0x004f0002; + mpp->frep = 0x004f0002 | ((mpp->nb_cpus - 1) << 8); mpp->veni = VENI; mpp->pint = 0x00000000; mpp->spve = 0x0000FFFF; @@ -1684,10 +1684,6 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus, {mpic_cpu_read, mpic_cpu_write, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE}, }; - /* XXX: for now, only one CPU is supported */ - if (nb_cpus != 1) - return NULL; - mpp = g_malloc0(sizeof(openpic_t)); for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) { -- 1.6.0.2