From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:43950) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RBixR-0001iF-4m for qemu-devel@nongnu.org; Thu, 06 Oct 2011 04:05:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RBixO-0000rT-1S for qemu-devel@nongnu.org; Thu, 06 Oct 2011 04:05:32 -0400 From: Alexander Graf Date: Thu, 6 Oct 2011 10:05:10 +0200 Message-Id: <1317888366-10509-9-git-send-email-agraf@suse.de> In-Reply-To: <1317888366-10509-1-git-send-email-agraf@suse.de> References: <1317888366-10509-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH 08/64] PPC: Set MPIC IDE for IPI to 0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , qemu-ppc@nongnu.org We use the IDE register with IPIs as a mask to keep track which processors have already acknowledged the respective interrupt. So we need to initialize it to 0 to make sure that it doesn't accidently fire an IPI on CPU0 when the first IPI is triggered. Reported-by: Elie Richa Signed-off-by: Alexander Graf --- v2 -> v3: - fix IDE IPI reset --- hw/openpic.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index 9710ac0..31ad175 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -1299,6 +1299,10 @@ static void mpic_reset (void *opaque) mpp->src[i].ipvp = 0x80800000; mpp->src[i].ide = 0x00000001; } + /* Set IDE for IPIs to 0 so we don't get spurious interrupts */ + for (i = mpp->irq_ipi0; i < (mpp->irq_ipi0 + MAX_IPI); i++) { + mpp->src[i].ide = 0; + } /* Initialise IRQ destinations */ for (i = 0; i < MAX_CPU; i++) { mpp->dst[i].pctp = 0x0000000F; -- 1.6.0.2