From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:52057) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RD5ZI-0005W2-6q for qemu-devel@nongnu.org; Sun, 09 Oct 2011 22:26:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RD5ZG-0002L1-V7 for qemu-devel@nongnu.org; Sun, 09 Oct 2011 22:26:16 -0400 Received: from [188.134.19.124] (port=59882 helo=octofox.metropolis) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RD5ZG-0002KV-Kb for qemu-devel@nongnu.org; Sun, 09 Oct 2011 22:26:14 -0400 From: Max Filippov Date: Mon, 10 Oct 2011 06:25:59 +0400 Message-Id: <1318213565-3268-2-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1318213565-3268-1-git-send-email-jcmvbkbc@gmail.com> References: <1318213565-3268-1-git-send-email-jcmvbkbc@gmail.com> Subject: [Qemu-devel] [PATCH 1/7] target-xtensa: increase xtensa options accuracy List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: jcmvbkbc@gmail.com - add separate options for each operation in the MISC_OP; - add an option for MULSH/MULUH; - put S32C1I under conditional store option. Signed-off-by: Max Filippov --- target-xtensa/cpu.h | 6 +++++- target-xtensa/translate.c | 14 +++++++------- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index b43e565..df168d5 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -52,9 +52,13 @@ enum { XTENSA_OPTION_EXTENDED_L32R, XTENSA_OPTION_16_BIT_IMUL, XTENSA_OPTION_32_BIT_IMUL, + XTENSA_OPTION_32_BIT_IMUL_HIGH, XTENSA_OPTION_32_BIT_IDIV, XTENSA_OPTION_MAC16, - XTENSA_OPTION_MISC_OP, + XTENSA_OPTION_MISC_OP_NSA, + XTENSA_OPTION_MISC_OP_MINMAX, + XTENSA_OPTION_MISC_OP_SEXT, + XTENSA_OPTION_MISC_OP_CLAMPS, XTENSA_OPTION_COPROCESSOR, XTENSA_OPTION_BOOLEAN, XTENSA_OPTION_FP_COPROCESSOR, diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 70bea62..1688bb2 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1116,13 +1116,13 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 14: /*NSAu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP); + HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); gen_window_check2(dc, RRR_S, RRR_T); gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]); break; case 15: /*NSAUu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP); + HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); gen_window_check2(dc, RRR_S, RRR_T); gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]); break; @@ -1434,7 +1434,7 @@ static void disas_xtensa_insn(DisasContext *dc) case 10: /*MULUHi*/ case 11: /*MULSHi*/ - HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL); + HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH); { TCGv_i64 r = tcg_temp_new_i64(); TCGv_i64 s = tcg_temp_new_i64(); @@ -1521,7 +1521,7 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 2: /*SEXTu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP); + HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT); gen_window_check2(dc, RRR_R, RRR_S); { int shift = 24 - RRR_T; @@ -1540,7 +1540,7 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 3: /*CLAMPSu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP); + HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS); gen_window_check2(dc, RRR_R, RRR_S); { TCGv_i32 tmp1 = tcg_temp_new_i32(); @@ -1568,7 +1568,7 @@ static void disas_xtensa_insn(DisasContext *dc) case 5: /*MAXu*/ case 6: /*MINUu*/ case 7: /*MAXUu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP); + HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX); gen_window_check3(dc, RRR_R, RRR_S, RRR_T); { static const TCGCond cond[] = { @@ -1921,7 +1921,7 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 14: /*S32C1Iy*/ - HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); + HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE); gen_window_check2(dc, RRI8_S, RRI8_T); { int label = gen_new_label(); -- 1.7.6.4