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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: blauwirbel@gmail.com
Subject: [Qemu-devel] [PATCH 14/21] target-sparc: Implement fpack{16, 32, fix}.
Date: Tue, 18 Oct 2011 11:50:36 -0700	[thread overview]
Message-ID: <1318963843-25100-15-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1318963843-25100-1-git-send-email-rth@twiddle.net>

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-sparc/helper.h     |    3 ++
 target-sparc/translate.c  |   21 ++++++++++++++-
 target-sparc/vis_helper.c |   64 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 87 insertions(+), 1 deletions(-)

diff --git a/target-sparc/helper.h b/target-sparc/helper.h
index 1a8e586..5c8d266 100644
--- a/target-sparc/helper.h
+++ b/target-sparc/helper.h
@@ -138,6 +138,9 @@ DEF_HELPER_FLAGS_2(fmuld8sux16, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(fmuld8ulx16, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(fexpand, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
 DEF_HELPER_FLAGS_3(pdist, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64, i64)
+DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_CONST | TCG_CALL_PURE, i32, i64, i64)
+DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64, i64)
+DEF_HELPER_FLAGS_2(fpackfix, TCG_CALL_CONST | TCG_CALL_PURE, i32, i64, i64)
 #define VIS_HELPER(name)                                                 \
     DEF_HELPER_FLAGS_2(f ## name ## 16, TCG_CALL_CONST | TCG_CALL_PURE,  \
                        i64, i64, i64)                                    \
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 0acb477..1edf255 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -4077,9 +4077,28 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
                     gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
                     break;
                 case 0x03a: /* VIS I fpack32 */
+                    CHECK_FPU_FEATURE(dc, VIS1);
+                    cpu_src1_64 = gen_load_fpr_D(dc, rs1);
+                    cpu_src2_64 = gen_load_fpr_D(dc, rs2);
+                    cpu_dst_64 = gen_dest_fpr_D();
+                    gen_helper_fpack32(cpu_dst_64, cpu_gsr,
+                                       cpu_src1_64, cpu_src2_64);
+                    gen_store_fpr_D(dc, rd, cpu_dst_64);
+                    break;
                 case 0x03b: /* VIS I fpack16 */
+                    CHECK_FPU_FEATURE(dc, VIS1);
+                    cpu_src1_64 = gen_load_fpr_D(dc, rs2);
+                    cpu_dst_32 = gen_dest_fpr_F();
+                    gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
+                    gen_store_fpr_F(dc, rd, cpu_dst_32);
+                    break;
                 case 0x03d: /* VIS I fpackfix */
-                    goto illegal_insn;
+                    CHECK_FPU_FEATURE(dc, VIS1);
+                    cpu_src1_64 = gen_load_fpr_D(dc, rs2);
+                    cpu_dst_32 = gen_dest_fpr_F();
+                    gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
+                    gen_store_fpr_F(dc, rd, cpu_dst_32);
+                    break;
                 case 0x03e: /* VIS I pdist */
                     CHECK_FPU_FEATURE(dc, VIS1);
                     gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
diff --git a/target-sparc/vis_helper.c b/target-sparc/vis_helper.c
index cd5d4a7..59ca8d7 100644
--- a/target-sparc/vis_helper.c
+++ b/target-sparc/vis_helper.c
@@ -417,3 +417,67 @@ uint64_t helper_pdist(uint64_t sum, uint64_t src1, uint64_t src2)
 
     return sum;
 }
+
+uint32_t helper_fpack16(uint64_t gsr, uint64_t rs2)
+{
+    int scale = (gsr >> 3) & 0xf;
+    uint32_t ret = 0;
+    int byte;
+
+    for (byte = 0; byte < 4; byte++) {
+        uint32_t val;
+        int16_t src = rs2 >> (byte * 16);
+        int32_t scaled = src << scale;
+        int32_t from_fixed = scaled >> 7;
+
+        val = (from_fixed < 0 ?  0 :
+               from_fixed > 255 ?  255 : from_fixed);
+
+        ret |= val << (8 * byte);
+    }
+
+    return ret;
+}
+
+uint64_t helper_fpack32(uint64_t gsr, uint64_t rs1, uint64_t rs2)
+{
+    int scale = (gsr >> 3) & 0x1f;
+    uint64_t ret = 0;
+    int word;
+
+    ret = (rs1 << 8) & ~(0x000000ff000000ffULL);
+    for (word = 0; word < 2; word++) {
+        uint64_t val;
+        int32_t src = rs2 >> (word * 32);
+        int64_t scaled = (int64_t)src << scale;
+        int64_t from_fixed = scaled >> 23;
+
+        val = (from_fixed < 0 ? 0 :
+               (from_fixed > 255) ? 255 : from_fixed);
+
+        ret |= val << (32 * word);
+    }
+
+    return ret;
+}
+
+uint32_t helper_fpackfix(uint64_t gsr, uint64_t rs2)
+{
+    int scale = (gsr >> 3) & 0x1f;
+    uint32_t ret = 0;
+    int word;
+
+    for (word = 0; word < 2; word++) {
+        uint32_t val;
+        int32_t src = rs2 >> (word * 32);
+        int64_t scaled = src << scale;
+        int64_t from_fixed = scaled >> 16;
+
+        val = (from_fixed < -32768 ? -32768 :
+               from_fixed > 32767 ?  32767 : from_fixed);
+
+        ret |= (val & 0xffff) << (word * 16);
+    }
+
+    return ret;
+}
-- 
1.7.6.4

  parent reply	other threads:[~2011-10-18 18:52 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-10-18 18:50 [Qemu-devel] [PATCH 00/21] Sparc FPU/VIS improvements Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 01/21] target-sparc: Add accessors for single-precision fpr access Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 02/21] target-sparc: Mark fprs dirty in store accessor Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 03/21] target-sparc: Add accessors for double-precision fpr access Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 04/21] target-sparc: Pass float64 parameters instead of dt0/1 temporaries Richard Henderson
2011-10-18 20:04   ` Blue Swirl
2011-10-18 20:07     ` Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 05/21] target-sparc: Make VIS helpers const when possible Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 06/21] target-sparc: Extract common code for floating-point operations Richard Henderson
2011-10-18 20:24   ` Blue Swirl
2011-10-18 22:21     ` Richard Henderson
2011-10-23 11:34       ` Blue Swirl
2011-10-18 18:50 ` [Qemu-devel] [PATCH 07/21] target-sparc: Extract float128 move to a function Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 08/21] target-sparc: Undo cpu_fpr rename Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 09/21] target-sparc: Change fpr representation to doubles Richard Henderson
2011-10-18 20:28   ` Blue Swirl
2011-10-18 22:25     ` Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 10/21] tcg: Optimize some forms of deposit Richard Henderson
2011-10-18 20:30   ` Blue Swirl
2011-10-18 22:27     ` Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 11/21] target-sparc: Do exceptions management fully inside the helpers Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 12/21] sparc-linux-user: Handle SIGILL Richard Henderson
2011-10-18 20:32   ` Blue Swirl
2011-10-18 22:27     ` Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 13/21] target-sparc: Implement PDIST Richard Henderson
2011-10-18 18:50 ` Richard Henderson [this message]
2011-10-18 18:50 ` [Qemu-devel] [PATCH 15/21] target-sparc: Implement EDGE* instructions Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 16/21] target-sparc: Implement ALIGNADDR* inline Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 17/21] target-sparc: Implement BMASK/BSHUFFLE Richard Henderson
2011-10-18 20:36   ` Blue Swirl
2011-10-18 18:50 ` [Qemu-devel] [PATCH 18/21] target-sparc: Tidy fpack32 Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 19/21] target-sparc: Implement FALIGNDATA inline Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 20/21] sparc-linux-user: Add some missing syscall numbers Richard Henderson
2011-10-18 18:50 ` [Qemu-devel] [PATCH 21/21] sparc-linux-user: Enable NPTL Richard Henderson
2011-10-18 19:50 ` [Qemu-devel] [PATCH 00/21] Sparc FPU/VIS improvements Blue Swirl
2011-10-18 20:03   ` Richard Henderson
2011-10-18 20:19     ` Blue Swirl

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