From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:42474) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RIRG8-00022G-Kd for qemu-devel@nongnu.org; Mon, 24 Oct 2011 16:36:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RIRG7-0005C8-IR for qemu-devel@nongnu.org; Mon, 24 Oct 2011 16:36:36 -0400 Received: from mail-wy0-f173.google.com ([74.125.82.173]:59127) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RIRG7-0005C2-Cd for qemu-devel@nongnu.org; Mon, 24 Oct 2011 16:36:35 -0400 Received: by wyh15 with SMTP id 15so7488114wyh.4 for ; Mon, 24 Oct 2011 13:36:34 -0700 (PDT) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= Date: Mon, 24 Oct 2011 22:38:20 +0200 Message-Id: <1319488713-3482-2-git-send-email-benoit.canet@gmail.com> In-Reply-To: <1319488713-3482-1-git-send-email-benoit.canet@gmail.com> References: <1319488713-3482-1-git-send-email-benoit.canet@gmail.com> Subject: [Qemu-devel] [PATCH 01/14] mst_fpga: convert to memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, =?UTF-8?q?Beno=C3=AEt=20Canet?= Signed-off-by: Benoit Canet --- hw/mst_fpga.c | 29 ++++++++++++----------------- 1 files changed, 12 insertions(+), 17 deletions(-) diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c index 7bcd5d7..cf9957b 100644 --- a/hw/mst_fpga.c +++ b/hw/mst_fpga.c @@ -34,6 +34,7 @@ typedef struct mst_irq_state{ SysBusDevice busdev; + MemoryRegion iomem; qemu_irq parent; @@ -86,8 +87,8 @@ mst_fpga_set_irq(void *opaque, int irq, int level) } -static uint32_t -mst_fpga_readb(void *opaque, target_phys_addr_t addr) +static uint64_t +mst_fpga_readb(void *opaque, target_phys_addr_t addr, unsigned size) { mst_irq_state *s = (mst_irq_state *) opaque; @@ -124,7 +125,8 @@ mst_fpga_readb(void *opaque, target_phys_addr_t addr) } static void -mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) +mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint64_t value, + unsigned size) { mst_irq_state *s = (mst_irq_state *) opaque; value &= 0xffffffff; @@ -175,17 +177,11 @@ mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) } } -static CPUReadMemoryFunc * const mst_fpga_readfn[] = { - mst_fpga_readb, - mst_fpga_readb, - mst_fpga_readb, +static const MemoryRegionOps mst_fpga_ops = { + .read = mst_fpga_readb, + .write = mst_fpga_writeb, + .endianness = DEVICE_NATIVE_ENDIAN, }; -static CPUWriteMemoryFunc * const mst_fpga_writefn[] = { - mst_fpga_writeb, - mst_fpga_writeb, - mst_fpga_writeb, -}; - static int mst_fpga_post_load(void *opaque, int version_id) { @@ -198,7 +194,6 @@ static int mst_fpga_post_load(void *opaque, int version_id) static int mst_fpga_init(SysBusDevice *dev) { mst_irq_state *s; - int iomemtype; s = FROM_SYSBUS(mst_irq_state, dev); @@ -210,9 +205,9 @@ static int mst_fpga_init(SysBusDevice *dev) /* alloc the external 16 irqs */ qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS); - iomemtype = cpu_register_io_memory(mst_fpga_readfn, - mst_fpga_writefn, s, DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x00100000, iomemtype); + memory_region_init_io(&s->iomem, &mst_fpga_ops, s, + "fpga", 0x00100000); + sysbus_init_mmio_region(dev, &s->iomem); return 0; } -- 1.7.4.1