From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:34575) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RJ4w0-0008TB-Bd for qemu-devel@nongnu.org; Wed, 26 Oct 2011 10:58:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RJ4vy-0007b5-Ep for qemu-devel@nongnu.org; Wed, 26 Oct 2011 10:58:28 -0400 Received: from mail-ww0-f53.google.com ([74.125.82.53]:48505) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RJ4vy-0007at-8j for qemu-devel@nongnu.org; Wed, 26 Oct 2011 10:58:26 -0400 Received: by wwi36 with SMTP id 36so2345784wwi.10 for ; Wed, 26 Oct 2011 07:58:25 -0700 (PDT) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= Date: Wed, 26 Oct 2011 16:56:36 +0200 Message-Id: <1319640996-26537-11-git-send-email-benoit.canet@gmail.com> In-Reply-To: <1319640996-26537-1-git-send-email-benoit.canet@gmail.com> References: <1319640996-26537-1-git-send-email-benoit.canet@gmail.com> Subject: [Qemu-devel] [PATCH 10/10] pxa2xx_lcd: convert to memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, =?UTF-8?q?Beno=C3=AEt=20Canet?= , avi@redhat.com Signed-off-by: Benoit Canet --- hw/pxa2xx_lcd.c | 30 +++++++++++++----------------- 1 files changed, 13 insertions(+), 17 deletions(-) diff --git a/hw/pxa2xx_lcd.c b/hw/pxa2xx_lcd.c index b73290c..2ab3c3b 100644 --- a/hw/pxa2xx_lcd.c +++ b/hw/pxa2xx_lcd.c @@ -14,6 +14,7 @@ /* FIXME: For graphic_rotate. Should probably be done in common code. */ #include "sysemu.h" #include "framebuffer.h" +#include "exec-memory.h" struct DMAChannel { target_phys_addr_t branch; @@ -30,6 +31,7 @@ struct DMAChannel { }; struct PXA2xxLCDState { + MemoryRegion iomem; qemu_irq irq; int irqlevel; @@ -315,7 +317,8 @@ static void pxa2xx_descriptor_load(PXA2xxLCDState *s) } } -static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset) +static uint64_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset, + unsigned size) { PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; int ch; @@ -408,8 +411,8 @@ static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset) return 0; } -static void pxa2xx_lcdc_write(void *opaque, - target_phys_addr_t offset, uint32_t value) +static void pxa2xx_lcdc_write(void *opaque, target_phys_addr_t offset, + uint64_t value, unsigned size) { PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; int ch; @@ -561,16 +564,10 @@ static void pxa2xx_lcdc_write(void *opaque, } } -static CPUReadMemoryFunc * const pxa2xx_lcdc_readfn[] = { - pxa2xx_lcdc_read, - pxa2xx_lcdc_read, - pxa2xx_lcdc_read -}; - -static CPUWriteMemoryFunc * const pxa2xx_lcdc_writefn[] = { - pxa2xx_lcdc_write, - pxa2xx_lcdc_write, - pxa2xx_lcdc_write +static const MemoryRegionOps pxa2xx_lcdc_ops = { + .read = pxa2xx_lcdc_read, + .write = pxa2xx_lcdc_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; /* Load new palette for a given DMA channel, convert to internal format */ @@ -983,7 +980,6 @@ static const VMStateDescription vmstate_pxa2xx_lcdc = { PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq) { - int iomemtype; PXA2xxLCDState *s; s = (PXA2xxLCDState *) g_malloc0(sizeof(PXA2xxLCDState)); @@ -992,9 +988,9 @@ PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq) pxa2xx_lcdc_orientation(s, graphic_rotate); - iomemtype = cpu_register_io_memory(pxa2xx_lcdc_readfn, - pxa2xx_lcdc_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x00100000, iomemtype); + memory_region_init_io(&s->iomem, &pxa2xx_lcdc_ops, s, + "lcd-controller", 0x00100000); + memory_region_add_subregion(get_system_memory(), base, &s->iomem); s->ds = graphic_console_init(pxa2xx_update_display, pxa2xx_invalidate_display, -- 1.7.4.1