From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:34348) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RJ4uk-00044B-Ka for qemu-devel@nongnu.org; Wed, 26 Oct 2011 10:57:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RJ4uj-0007RO-2U for qemu-devel@nongnu.org; Wed, 26 Oct 2011 10:57:10 -0400 Received: from mail-ww0-f53.google.com ([74.125.82.53]:40704) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RJ4ui-0007RD-SX for qemu-devel@nongnu.org; Wed, 26 Oct 2011 10:57:09 -0400 Received: by wwi36 with SMTP id 36so2343810wwi.10 for ; Wed, 26 Oct 2011 07:57:07 -0700 (PDT) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= Date: Wed, 26 Oct 2011 16:56:27 +0200 Message-Id: <1319640996-26537-2-git-send-email-benoit.canet@gmail.com> In-Reply-To: <1319640996-26537-1-git-send-email-benoit.canet@gmail.com> References: <1319640996-26537-1-git-send-email-benoit.canet@gmail.com> Subject: [Qemu-devel] [PATCH 01/10] pxa2xx_gpio: convert to memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, =?UTF-8?q?Beno=C3=AEt=20Canet?= , avi@redhat.com Signed-off-by: Benoit Canet --- hw/pxa2xx_gpio.c | 29 +++++++++++------------------ 1 files changed, 11 insertions(+), 18 deletions(-) diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c index 200b0cf..f7464fe 100644 --- a/hw/pxa2xx_gpio.c +++ b/hw/pxa2xx_gpio.c @@ -16,6 +16,7 @@ typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo; struct PXA2xxGPIOInfo { SysBusDevice busdev; + MemoryRegion iomem; qemu_irq irq0, irq1, irqX; int lines; int ncpu; @@ -137,7 +138,8 @@ static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) { } } -static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset) +static uint64_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset, + unsigned size) { PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; uint32_t ret; @@ -188,8 +190,8 @@ static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset) return 0; } -static void pxa2xx_gpio_write(void *opaque, - target_phys_addr_t offset, uint32_t value) +static void pxa2xx_gpio_write(void *opaque, target_phys_addr_t offset, + uint64_t value, unsigned size) { PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; int bank; @@ -240,16 +242,10 @@ static void pxa2xx_gpio_write(void *opaque, } } -static CPUReadMemoryFunc * const pxa2xx_gpio_readfn[] = { - pxa2xx_gpio_read, - pxa2xx_gpio_read, - pxa2xx_gpio_read -}; - -static CPUWriteMemoryFunc * const pxa2xx_gpio_writefn[] = { - pxa2xx_gpio_write, - pxa2xx_gpio_write, - pxa2xx_gpio_write +static const MemoryRegionOps pxa_gpio_ops = { + .read = pxa2xx_gpio_read, + .write = pxa2xx_gpio_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; DeviceState *pxa2xx_gpio_init(target_phys_addr_t base, @@ -275,7 +271,6 @@ DeviceState *pxa2xx_gpio_init(target_phys_addr_t base, static int pxa2xx_gpio_initfn(SysBusDevice *dev) { - int iomemtype; PXA2xxGPIOInfo *s; s = FROM_SYSBUS(PXA2xxGPIOInfo, dev); @@ -285,10 +280,8 @@ static int pxa2xx_gpio_initfn(SysBusDevice *dev) qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines); qdev_init_gpio_out(&dev->qdev, s->handler, s->lines); - iomemtype = cpu_register_io_memory(pxa2xx_gpio_readfn, - pxa2xx_gpio_writefn, s, DEVICE_NATIVE_ENDIAN); - - sysbus_init_mmio(dev, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &pxa_gpio_ops, s, "gpio", 0x1000); + sysbus_init_mmio_region(dev, &s->iomem); sysbus_init_irq(dev, &s->irq0); sysbus_init_irq(dev, &s->irq1); sysbus_init_irq(dev, &s->irqX); -- 1.7.4.1