From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:34386) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RJ4uy-0004sO-E4 for qemu-devel@nongnu.org; Wed, 26 Oct 2011 10:57:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RJ4ux-0007T2-9n for qemu-devel@nongnu.org; Wed, 26 Oct 2011 10:57:24 -0400 Received: from mail-wy0-f173.google.com ([74.125.82.173]:47822) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RJ4ux-0007Q1-3s for qemu-devel@nongnu.org; Wed, 26 Oct 2011 10:57:23 -0400 Received: by mail-wy0-f173.google.com with SMTP id 15so1940368wyh.4 for ; Wed, 26 Oct 2011 07:57:22 -0700 (PDT) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= Date: Wed, 26 Oct 2011 16:56:29 +0200 Message-Id: <1319640996-26537-4-git-send-email-benoit.canet@gmail.com> In-Reply-To: <1319640996-26537-1-git-send-email-benoit.canet@gmail.com> References: <1319640996-26537-1-git-send-email-benoit.canet@gmail.com> Subject: [Qemu-devel] [PATCH 03/10] pxa2xx_pcmcia.c: convert attribute memory space to memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, =?UTF-8?q?Beno=C3=AEt=20Canet?= , avi@redhat.com Signed-off-by: Benoit Canet --- hw/pxa2xx_pcmcia.c | 31 ++++++++++++++----------------- 1 files changed, 14 insertions(+), 17 deletions(-) diff --git a/hw/pxa2xx_pcmcia.c b/hw/pxa2xx_pcmcia.c index 51ed72a..94811fc 100644 --- a/hw/pxa2xx_pcmcia.c +++ b/hw/pxa2xx_pcmcia.c @@ -12,10 +12,12 @@ #include "pxa.h" #include "exec-memory.h" + struct PXA2xxPCMCIAState { PCMCIASocket slot; PCMCIACardState *card; MemoryRegion common_iomem; + MemoryRegion attr_iomem; qemu_irq irq; qemu_irq cd_irq; @@ -43,8 +45,8 @@ static void pxa2xx_pcmcia_common_write(void *opaque, target_phys_addr_t offset, } } -static uint32_t pxa2xx_pcmcia_attr_read(void *opaque, - target_phys_addr_t offset) +static uint64_t pxa2xx_pcmcia_attr_read(void *opaque, + target_phys_addr_t offset, unsigned size) { PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; @@ -55,8 +57,8 @@ static uint32_t pxa2xx_pcmcia_attr_read(void *opaque, return 0; } -static void pxa2xx_pcmcia_attr_write(void *opaque, - target_phys_addr_t offset, uint32_t value) +static void pxa2xx_pcmcia_attr_write(void *opaque, target_phys_addr_t offset, + uint64_t value, unsigned size) { PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; @@ -93,16 +95,10 @@ static const MemoryRegionOps pxa2xx_pcmcia_common_ops = { .endianness = DEVICE_NATIVE_ENDIAN }; -static CPUReadMemoryFunc * const pxa2xx_pcmcia_attr_readfn[] = { - pxa2xx_pcmcia_attr_read, - pxa2xx_pcmcia_attr_read, - pxa2xx_pcmcia_attr_read, -}; - -static CPUWriteMemoryFunc * const pxa2xx_pcmcia_attr_writefn[] = { - pxa2xx_pcmcia_attr_write, - pxa2xx_pcmcia_attr_write, - pxa2xx_pcmcia_attr_write, +static const MemoryRegionOps pxa2xx_pcmcia_attr_ops = { + .read = pxa2xx_pcmcia_attr_read, + .write = pxa2xx_pcmcia_attr_write, + .endianness = DEVICE_NATIVE_ENDIAN }; static CPUReadMemoryFunc * const pxa2xx_pcmcia_io_readfn[] = { @@ -142,9 +138,10 @@ PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base) /* Then next 64 MB is reserved */ /* Socket Attribute Memory Space */ - iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_attr_readfn, - pxa2xx_pcmcia_attr_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base | 0x08000000, 0x04000000, iomemtype); + memory_region_init_io(&s->attr_iomem, &pxa2xx_pcmcia_attr_ops, s, + "pcmcia_attribute", 0x04000000); + memory_region_add_subregion(get_system_memory(), base | 0x08000000, + &s->attr_iomem); /* Socket Common Memory Space */ memory_region_init_io(&s->common_iomem, &pxa2xx_pcmcia_common_ops, s, -- 1.7.4.1