From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:34401) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RJ4v3-00057k-Lv for qemu-devel@nongnu.org; Wed, 26 Oct 2011 10:57:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RJ4v2-0007Te-BS for qemu-devel@nongnu.org; Wed, 26 Oct 2011 10:57:29 -0400 Received: from mail-wy0-f173.google.com ([74.125.82.173]:47822) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RJ4v1-0007Q1-Qx for qemu-devel@nongnu.org; Wed, 26 Oct 2011 10:57:28 -0400 Received: by mail-wy0-f173.google.com with SMTP id 15so1940368wyh.4 for ; Wed, 26 Oct 2011 07:57:27 -0700 (PDT) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= Date: Wed, 26 Oct 2011 16:56:30 +0200 Message-Id: <1319640996-26537-5-git-send-email-benoit.canet@gmail.com> In-Reply-To: <1319640996-26537-1-git-send-email-benoit.canet@gmail.com> References: <1319640996-26537-1-git-send-email-benoit.canet@gmail.com> Subject: [Qemu-devel] [PATCH 04/10] pxa2xx_pcmcia.c: convert io memory space to memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, =?UTF-8?q?Beno=C3=AEt=20Canet?= , avi@redhat.com Signed-off-by: Benoit Canet --- hw/pxa2xx_pcmcia.c | 31 +++++++++++++------------------ 1 files changed, 13 insertions(+), 18 deletions(-) diff --git a/hw/pxa2xx_pcmcia.c b/hw/pxa2xx_pcmcia.c index 94811fc..f428bd1 100644 --- a/hw/pxa2xx_pcmcia.c +++ b/hw/pxa2xx_pcmcia.c @@ -18,6 +18,7 @@ struct PXA2xxPCMCIAState { PCMCIACardState *card; MemoryRegion common_iomem; MemoryRegion attr_iomem; + MemoryRegion iomem; qemu_irq irq; qemu_irq cd_irq; @@ -67,8 +68,8 @@ static void pxa2xx_pcmcia_attr_write(void *opaque, target_phys_addr_t offset, } } -static uint32_t pxa2xx_pcmcia_io_read(void *opaque, - target_phys_addr_t offset) +static uint64_t pxa2xx_pcmcia_io_read(void *opaque, + target_phys_addr_t offset, unsigned size) { PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; @@ -79,8 +80,8 @@ static uint32_t pxa2xx_pcmcia_io_read(void *opaque, return 0; } -static void pxa2xx_pcmcia_io_write(void *opaque, - target_phys_addr_t offset, uint32_t value) +static void pxa2xx_pcmcia_io_write(void *opaque, target_phys_addr_t offset, + uint64_t value, unsigned size) { PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque; @@ -101,16 +102,10 @@ static const MemoryRegionOps pxa2xx_pcmcia_attr_ops = { .endianness = DEVICE_NATIVE_ENDIAN }; -static CPUReadMemoryFunc * const pxa2xx_pcmcia_io_readfn[] = { - pxa2xx_pcmcia_io_read, - pxa2xx_pcmcia_io_read, - pxa2xx_pcmcia_io_read, -}; - -static CPUWriteMemoryFunc * const pxa2xx_pcmcia_io_writefn[] = { - pxa2xx_pcmcia_io_write, - pxa2xx_pcmcia_io_write, - pxa2xx_pcmcia_io_write, +static const MemoryRegionOps pxa2xx_pcmcia_io_ops = { + .read = pxa2xx_pcmcia_io_read, + .write = pxa2xx_pcmcia_io_write, + .endianness = DEVICE_NATIVE_ENDIAN }; static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level) @@ -124,16 +119,16 @@ static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level) PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base) { - int iomemtype; PXA2xxPCMCIAState *s; s = (PXA2xxPCMCIAState *) g_malloc0(sizeof(PXA2xxPCMCIAState)); /* Socket I/O Memory Space */ - iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_io_readfn, - pxa2xx_pcmcia_io_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base | 0x00000000, 0x04000000, iomemtype); + memory_region_init_io(&s->iomem, &pxa2xx_pcmcia_io_ops, s, + "pcmcia_io", 0x04000000); + memory_region_add_subregion(get_system_memory(), base | 0x00000000, + &s->iomem); /* Then next 64 MB is reserved */ -- 1.7.4.1