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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: blauwirbel@gmail.com
Subject: [Qemu-devel] [PATCH 11/16] target-sparc: Implement PDIST.
Date: Wed, 26 Oct 2011 14:15:31 -0700	[thread overview]
Message-ID: <1319663736-7545-12-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1319663736-7545-1-git-send-email-rth@twiddle.net>

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-sparc/helper.h     |    1 +
 target-sparc/translate.c  |   21 +++++++++++++++++++--
 target-sparc/vis_helper.c |   21 +++++++++++++++++++++
 3 files changed, 41 insertions(+), 2 deletions(-)

diff --git a/target-sparc/helper.h b/target-sparc/helper.h
index 22fb8ef..22f9dce 100644
--- a/target-sparc/helper.h
+++ b/target-sparc/helper.h
@@ -137,6 +137,7 @@ DEF_HELPER_FLAGS_2(fmul8ulx16, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(fmuld8sux16, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(fmuld8ulx16, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(fexpand, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
+DEF_HELPER_FLAGS_3(pdist, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64, i64)
 #define VIS_HELPER(name)                                                 \
     DEF_HELPER_FLAGS_2(f ## name ## 16, TCG_CALL_CONST | TCG_CALL_PURE,  \
                        i64, i64, i64)                                    \
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 0b9ace3..2646aaf 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -1738,6 +1738,21 @@ static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
 
     gen_store_fpr_D(dc, rd, dst);
 }
+
+static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
+                           void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
+{
+    TCGv_i64 dst, src0, src1, src2;
+
+    src1 = gen_load_fpr_D(dc, rs1);
+    src2 = gen_load_fpr_D(dc, rs2);
+    src0 = gen_load_fpr_D(dc, rd);
+    dst = gen_dest_fpr_D();
+
+    gen(dst, src0, src1, src2);
+
+    gen_store_fpr_D(dc, rd, dst);
+}
 #endif
 
 static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
@@ -4059,9 +4074,11 @@ static void disas_sparc_insn(DisasContext * dc)
                 case 0x03a: /* VIS I fpack32 */
                 case 0x03b: /* VIS I fpack16 */
                 case 0x03d: /* VIS I fpackfix */
-                case 0x03e: /* VIS I pdist */
-                    // XXX
                     goto illegal_insn;
+                case 0x03e: /* VIS I pdist */
+                    CHECK_FPU_FEATURE(dc, VIS1);
+                    gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
+                    break;
                 case 0x048: /* VIS I faligndata */
                     CHECK_FPU_FEATURE(dc, VIS1);
                     cpu_src1_64 = gen_load_fpr_D(dc, rs1);
diff --git a/target-sparc/vis_helper.c b/target-sparc/vis_helper.c
index 39c8d9a..cd5d4a7 100644
--- a/target-sparc/vis_helper.c
+++ b/target-sparc/vis_helper.c
@@ -396,3 +396,24 @@ VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
 VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
 VIS_CMPHELPER(helper_fcmple, FCMPLE)
 VIS_CMPHELPER(helper_fcmpne, FCMPNE)
+
+uint64_t helper_pdist(uint64_t sum, uint64_t src1, uint64_t src2)
+{
+    int i;
+    for (i = 0; i < 8; i++) {
+        int s1, s2;
+
+        s1 = (src1 >> (56 - (i * 8))) & 0xff;
+        s2 = (src2 >> (56 - (i * 8))) & 0xff;
+
+        /* Absolute value of difference. */
+        s1 -= s2;
+        if (s1 < 0) {
+            s1 = -s1;
+        }
+
+        sum += s1;
+    }
+
+    return sum;
+}
-- 
1.7.6.4

  parent reply	other threads:[~2011-10-26 21:16 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-10-26 21:15 [Qemu-devel] [PATCH v2 00/16] Sparc FPU/VIS improvements Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 01/16] target-sparc: Add accessors for single-precision fpr access Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 02/16] target-sparc: Mark fprs dirty in store accessor Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 03/16] target-sparc: Add accessors for double-precision fpr access Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 04/16] target-sparc: Pass float64 parameters instead of dt0/1 temporaries Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 05/16] target-sparc: Make FPU/VIS helpers const when possible Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 06/16] target-sparc: Extract common code for floating-point operations Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 07/16] target-sparc: Extract float128 move to a function Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 08/16] target-sparc: Undo cpu_fpr rename Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 09/16] target-sparc: Change fpr representation to doubles Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 10/16] target-sparc: Do exceptions management fully inside the helpers Richard Henderson
2011-10-26 21:15 ` Richard Henderson [this message]
2011-10-26 21:15 ` [Qemu-devel] [PATCH 12/16] target-sparc: Implement fpack{16, 32, fix} Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 13/16] target-sparc: Implement EDGE* instructions Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 14/16] target-sparc: Implement ALIGNADDR* inline Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 15/16] target-sparc: Implement BMASK/BSHUFFLE Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 16/16] target-sparc: Implement FALIGNDATA inline Richard Henderson
2011-10-26 21:18 ` [Qemu-devel] [PATCH v2 00/16] Sparc FPU/VIS improvements Richard Henderson
2011-10-27 20:59   ` Blue Swirl

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