From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: blauwirbel@gmail.com
Subject: [Qemu-devel] [PATCH 07/16] target-sparc: Extract float128 move to a function.
Date: Wed, 26 Oct 2011 14:15:27 -0700 [thread overview]
Message-ID: <1319663736-7545-8-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1319663736-7545-1-git-send-email-rth@twiddle.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 50 ++++++++++++++++-----------------------------
1 files changed, 18 insertions(+), 32 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 6c13f1c..106b406 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -222,6 +222,20 @@ static void gen_op_store_QT0_fpr(unsigned int dst)
offsetof(CPU_QuadU, l.lowest));
}
+#ifdef TARGET_SPARC64
+static void gen_move_Q(int rd, int rs)
+{
+ rd = QFPREG(rd);
+ rs = QFPREG(rs);
+
+ tcg_gen_mov_i32(cpu__fpr[rd], cpu__fpr[rs]);
+ tcg_gen_mov_i32(cpu__fpr[rd + 1], cpu__fpr[rs + 1]);
+ tcg_gen_mov_i32(cpu__fpr[rd + 2], cpu__fpr[rs + 2]);
+ tcg_gen_mov_i32(cpu__fpr[rd + 3], cpu__fpr[rs + 3]);
+ gen_update_fprs_dirty(rd);
+}
+#endif
+
/* moves */
#ifdef CONFIG_USER_ONLY
#define supervisor(dc) 0
@@ -2831,15 +2845,7 @@ static void disas_sparc_insn(DisasContext * dc)
break;
case 0x3: /* V9 fmovq */
CHECK_FPU_FEATURE(dc, FLOAT128);
- tcg_gen_mov_i32(cpu__fpr[QFPREG(rd)],
- cpu__fpr[QFPREG(rs2)]);
- tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 1],
- cpu__fpr[QFPREG(rs2) + 1]);
- tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 2],
- cpu__fpr[QFPREG(rs2) + 2]);
- tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 3],
- cpu__fpr[QFPREG(rs2) + 3]);
- gen_update_fprs_dirty(QFPREG(rd));
+ gen_move_Q(rd, rs2);
break;
case 0x6: /* V9 fnegd */
gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
@@ -2924,11 +2930,7 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1 = get_src1(insn, cpu_src1);
tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
0, l1);
- tcg_gen_mov_i32(cpu__fpr[QFPREG(rd)], cpu__fpr[QFPREG(rs2)]);
- tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 1], cpu__fpr[QFPREG(rs2) + 1]);
- tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 2], cpu__fpr[QFPREG(rs2) + 2]);
- tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 3], cpu__fpr[QFPREG(rs2) + 3]);
- gen_update_fprs_dirty(QFPREG(rd));
+ gen_move_Q(rd, rs2);
gen_set_label(l1);
break;
}
@@ -2978,15 +2980,7 @@ static void disas_sparc_insn(DisasContext * dc)
gen_fcond(r_cond, fcc, cond); \
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
0, l1); \
- tcg_gen_mov_i32(cpu__fpr[QFPREG(rd)], \
- cpu__fpr[QFPREG(rs2)]); \
- tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 1], \
- cpu__fpr[QFPREG(rs2) + 1]); \
- tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 2], \
- cpu__fpr[QFPREG(rs2) + 2]); \
- tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 3], \
- cpu__fpr[QFPREG(rs2) + 3]); \
- gen_update_fprs_dirty(QFPREG(rd)); \
+ gen_move_Q(rd, rs2); \
gen_set_label(l1); \
tcg_temp_free(r_cond); \
}
@@ -3077,15 +3071,7 @@ static void disas_sparc_insn(DisasContext * dc)
gen_cond(r_cond, icc, cond, dc); \
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
0, l1); \
- tcg_gen_mov_i32(cpu__fpr[QFPREG(rd)], \
- cpu__fpr[QFPREG(rs2)]); \
- tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 1], \
- cpu__fpr[QFPREG(rs2) + 1]); \
- tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 2], \
- cpu__fpr[QFPREG(rs2) + 2]); \
- tcg_gen_mov_i32(cpu__fpr[QFPREG(rd) + 3], \
- cpu__fpr[QFPREG(rs2) + 3]); \
- gen_update_fprs_dirty(QFPREG(rd)); \
+ gen_move_Q(rd, rs2); \
gen_set_label(l1); \
tcg_temp_free(r_cond); \
}
--
1.7.6.4
next prev parent reply other threads:[~2011-10-26 21:16 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-26 21:15 [Qemu-devel] [PATCH v2 00/16] Sparc FPU/VIS improvements Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 01/16] target-sparc: Add accessors for single-precision fpr access Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 02/16] target-sparc: Mark fprs dirty in store accessor Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 03/16] target-sparc: Add accessors for double-precision fpr access Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 04/16] target-sparc: Pass float64 parameters instead of dt0/1 temporaries Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 05/16] target-sparc: Make FPU/VIS helpers const when possible Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 06/16] target-sparc: Extract common code for floating-point operations Richard Henderson
2011-10-26 21:15 ` Richard Henderson [this message]
2011-10-26 21:15 ` [Qemu-devel] [PATCH 08/16] target-sparc: Undo cpu_fpr rename Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 09/16] target-sparc: Change fpr representation to doubles Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 10/16] target-sparc: Do exceptions management fully inside the helpers Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 11/16] target-sparc: Implement PDIST Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 12/16] target-sparc: Implement fpack{16, 32, fix} Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 13/16] target-sparc: Implement EDGE* instructions Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 14/16] target-sparc: Implement ALIGNADDR* inline Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 15/16] target-sparc: Implement BMASK/BSHUFFLE Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 16/16] target-sparc: Implement FALIGNDATA inline Richard Henderson
2011-10-26 21:18 ` [Qemu-devel] [PATCH v2 00/16] Sparc FPU/VIS improvements Richard Henderson
2011-10-27 20:59 ` Blue Swirl
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