From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: blauwirbel@gmail.com
Subject: [Qemu-devel] [PATCH 08/16] target-sparc: Undo cpu_fpr rename.
Date: Wed, 26 Oct 2011 14:15:28 -0700 [thread overview]
Message-ID: <1319663736-7545-9-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1319663736-7545-1-git-send-email-rth@twiddle.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 56 +++++++++++++++++++++++-----------------------
1 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 106b406..0b95b64 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -63,7 +63,7 @@ static TCGv cpu_tmp0;
static TCGv_i32 cpu_tmp32;
static TCGv_i64 cpu_tmp64;
/* Floating point registers */
-static TCGv_i32 cpu__fpr[TARGET_FPREGS];
+static TCGv_i32 cpu_fpr[TARGET_FPREGS];
static target_ulong gen_opc_npc[OPC_BUF_SIZE];
static target_ulong gen_opc_jump_pc[2];
@@ -126,12 +126,12 @@ static inline void gen_update_fprs_dirty(int rd)
/* floating point registers moves */
static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
{
- return cpu__fpr[src];
+ return cpu_fpr[src];
}
static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
{
- tcg_gen_mov_i32(cpu__fpr[dst], v);
+ tcg_gen_mov_i32(cpu_fpr[dst], v);
gen_update_fprs_dirty(dst);
}
@@ -146,13 +146,13 @@ static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
src = DFPREG(src);
#if TCG_TARGET_REG_BITS == 32
- tcg_gen_mov_i32(TCGV_HIGH(ret), cpu__fpr[src]);
- tcg_gen_mov_i32(TCGV_LOW(ret), cpu__fpr[src + 1]);
+ tcg_gen_mov_i32(TCGV_HIGH(ret), cpu_fpr[src]);
+ tcg_gen_mov_i32(TCGV_LOW(ret), cpu_fpr[src + 1]);
#else
{
TCGv_i64 t = tcg_temp_new_i64();
- tcg_gen_extu_i32_i64(ret, cpu__fpr[src]);
- tcg_gen_extu_i32_i64(t, cpu__fpr[src + 1]);
+ tcg_gen_extu_i32_i64(ret, cpu_fpr[src]);
+ tcg_gen_extu_i32_i64(t, cpu_fpr[src + 1]);
tcg_gen_shli_i64(ret, ret, 32);
tcg_gen_or_i64(ret, ret, t);
tcg_temp_free_i64(t);
@@ -173,9 +173,9 @@ static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
tcg_gen_mov_i32(cpu__fpu[dst], TCGV_HIGH(v));
tcg_gen_mov_i32(cpu__fpu[dst + 1], TCGV_LOW(v));
#else
- tcg_gen_trunc_i64_i32(cpu__fpr[dst + 1], v);
+ tcg_gen_trunc_i64_i32(cpu_fpr[dst + 1], v);
tcg_gen_shri_i64(v, v, 32);
- tcg_gen_trunc_i64_i32(cpu__fpr[dst], v);
+ tcg_gen_trunc_i64_i32(cpu_fpr[dst], v);
#endif
gen_update_fprs_dirty(dst);
@@ -188,37 +188,37 @@ static TCGv_i64 gen_dest_fpr_D(void)
static void gen_op_load_fpr_QT0(unsigned int src)
{
- tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, l.upmost));
- tcg_gen_st_i32(cpu__fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, l.upper));
- tcg_gen_st_i32(cpu__fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, l.lower));
- tcg_gen_st_i32(cpu__fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, l.lowest));
}
static void gen_op_load_fpr_QT1(unsigned int src)
{
- tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) +
+ tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) +
offsetof(CPU_QuadU, l.upmost));
- tcg_gen_st_i32(cpu__fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
+ tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
offsetof(CPU_QuadU, l.upper));
- tcg_gen_st_i32(cpu__fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +
+ tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +
offsetof(CPU_QuadU, l.lower));
- tcg_gen_st_i32(cpu__fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +
+ tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +
offsetof(CPU_QuadU, l.lowest));
}
static void gen_op_store_QT0_fpr(unsigned int dst)
{
- tcg_gen_ld_i32(cpu__fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, l.upmost));
- tcg_gen_ld_i32(cpu__fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, l.upper));
- tcg_gen_ld_i32(cpu__fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, l.lower));
- tcg_gen_ld_i32(cpu__fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, l.lowest));
}
@@ -228,10 +228,10 @@ static void gen_move_Q(int rd, int rs)
rd = QFPREG(rd);
rs = QFPREG(rs);
- tcg_gen_mov_i32(cpu__fpr[rd], cpu__fpr[rs]);
- tcg_gen_mov_i32(cpu__fpr[rd + 1], cpu__fpr[rs + 1]);
- tcg_gen_mov_i32(cpu__fpr[rd + 2], cpu__fpr[rs + 2]);
- tcg_gen_mov_i32(cpu__fpr[rd + 3], cpu__fpr[rs + 3]);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs]);
+ tcg_gen_mov_i32(cpu_fpr[rd + 1], cpu_fpr[rs + 1]);
+ tcg_gen_mov_i32(cpu_fpr[rd + 2], cpu_fpr[rs + 2]);
+ tcg_gen_mov_i32(cpu_fpr[rd + 3], cpu_fpr[rs + 3]);
gen_update_fprs_dirty(rd);
}
#endif
@@ -5251,9 +5251,9 @@ void gen_intermediate_code_init(CPUSPARCState *env)
offsetof(CPUState, gregs[i]),
gregnames[i]);
for (i = 0; i < TARGET_FPREGS; i++)
- cpu__fpr[i] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, fpr[i]),
- fregnames[i]);
+ cpu_fpr[i] = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUState, fpr[i]),
+ fregnames[i]);
/* register helpers */
--
1.7.6.4
next prev parent reply other threads:[~2011-10-26 21:16 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-26 21:15 [Qemu-devel] [PATCH v2 00/16] Sparc FPU/VIS improvements Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 01/16] target-sparc: Add accessors for single-precision fpr access Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 02/16] target-sparc: Mark fprs dirty in store accessor Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 03/16] target-sparc: Add accessors for double-precision fpr access Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 04/16] target-sparc: Pass float64 parameters instead of dt0/1 temporaries Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 05/16] target-sparc: Make FPU/VIS helpers const when possible Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 06/16] target-sparc: Extract common code for floating-point operations Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 07/16] target-sparc: Extract float128 move to a function Richard Henderson
2011-10-26 21:15 ` Richard Henderson [this message]
2011-10-26 21:15 ` [Qemu-devel] [PATCH 09/16] target-sparc: Change fpr representation to doubles Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 10/16] target-sparc: Do exceptions management fully inside the helpers Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 11/16] target-sparc: Implement PDIST Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 12/16] target-sparc: Implement fpack{16, 32, fix} Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 13/16] target-sparc: Implement EDGE* instructions Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 14/16] target-sparc: Implement ALIGNADDR* inline Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 15/16] target-sparc: Implement BMASK/BSHUFFLE Richard Henderson
2011-10-26 21:15 ` [Qemu-devel] [PATCH 16/16] target-sparc: Implement FALIGNDATA inline Richard Henderson
2011-10-26 21:18 ` [Qemu-devel] [PATCH v2 00/16] Sparc FPU/VIS improvements Richard Henderson
2011-10-27 20:59 ` Blue Swirl
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