From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:55512) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RKWSl-00068f-2Y for qemu-devel@nongnu.org; Sun, 30 Oct 2011 10:34:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RKWSg-0003tb-AF for qemu-devel@nongnu.org; Sun, 30 Oct 2011 10:34:14 -0400 Received: from mx1.redhat.com ([209.132.183.28]:53730) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RKWSf-0003sb-8i for qemu-devel@nongnu.org; Sun, 30 Oct 2011 10:34:09 -0400 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p9UEY8lH012198 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Sun, 30 Oct 2011 10:34:08 -0400 Received: from cleopatra.tlv.redhat.com (cleopatra.tlv.redhat.com [10.35.255.11]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id p9UEY5JE028992 for ; Sun, 30 Oct 2011 10:34:08 -0400 From: Avi Kivity Date: Sun, 30 Oct 2011 16:33:47 +0200 Message-Id: <1319985234-32371-11-git-send-email-avi@redhat.com> In-Reply-To: <1319985234-32371-1-git-send-email-avi@redhat.com> References: <1319985234-32371-1-git-send-email-avi@redhat.com> Subject: [Qemu-devel] [PATCH 10/17] pl022: convert to memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Avi Kivity --- hw/pl022.c | 29 +++++++++++------------------ 1 files changed, 11 insertions(+), 18 deletions(-) diff --git a/hw/pl022.c b/hw/pl022.c index 9a1cb71..e0cf2b0 100644 --- a/hw/pl022.c +++ b/hw/pl022.c @@ -42,6 +42,7 @@ typedef struct { SysBusDevice busdev; + MemoryRegion iomem; uint32_t cr0; uint32_t cr1; uint32_t bitmask; @@ -130,7 +131,8 @@ static void pl022_xfer(pl022_state *s) pl022_update(s); } -static uint32_t pl022_read(void *opaque, target_phys_addr_t offset) +static uint64_t pl022_read(void *opaque, target_phys_addr_t offset, + unsigned size) { pl022_state *s = (pl022_state *)opaque; int val; @@ -173,7 +175,7 @@ static uint32_t pl022_read(void *opaque, target_phys_addr_t offset) } static void pl022_write(void *opaque, target_phys_addr_t offset, - uint32_t value) + uint64_t value, unsigned size) { pl022_state *s = (pl022_state *)opaque; @@ -193,7 +195,7 @@ static void pl022_write(void *opaque, target_phys_addr_t offset, break; case 0x08: /* DR */ if (s->tx_fifo_len < 8) { - DPRINTF("TX %02x\n", value); + DPRINTF("TX %02x\n", (unsigned)value); s->tx_fifo[s->tx_fifo_head] = value & s->bitmask; s->tx_fifo_head = (s->tx_fifo_head + 1) & 7; s->tx_fifo_len++; @@ -227,16 +229,10 @@ static void pl022_reset(pl022_state *s) s->sr = PL022_SR_TFE | PL022_SR_TNF; } -static CPUReadMemoryFunc * const pl022_readfn[] = { - pl022_read, - pl022_read, - pl022_read -}; - -static CPUWriteMemoryFunc * const pl022_writefn[] = { - pl022_write, - pl022_write, - pl022_write +static const MemoryRegionOps pl022_ops = { + .read = pl022_read, + .write = pl022_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static const VMStateDescription vmstate_pl022 = { @@ -279,12 +275,9 @@ static void pl022_reset(pl022_state *s) static int pl022_init(SysBusDevice *dev) { pl022_state *s = FROM_SYSBUS(pl022_state, dev); - int iomemtype; - iomemtype = cpu_register_io_memory(pl022_readfn, - pl022_writefn, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &pl022_ops, s, "pl022", 0x1000); + sysbus_init_mmio_region(dev, &s->iomem); sysbus_init_irq(dev, &s->irq); s->ssi = ssi_create_bus(&dev->qdev, "ssi"); pl022_reset(s); -- 1.7.6.3