From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:41531) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ROBZ4-0006nu-V2 for qemu-devel@nongnu.org; Wed, 09 Nov 2011 12:03:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ROBZ0-0000Md-04 for qemu-devel@nongnu.org; Wed, 09 Nov 2011 12:03:54 -0500 Received: from mail-wy0-f173.google.com ([74.125.82.173]:44832) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ROBYz-0000MH-QP for qemu-devel@nongnu.org; Wed, 09 Nov 2011 12:03:49 -0500 Received: by mail-wy0-f173.google.com with SMTP id 22so1977063wyh.4 for ; Wed, 09 Nov 2011 09:03:49 -0800 (PST) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= Date: Wed, 9 Nov 2011 18:03:43 +0100 Message-Id: <1320858224-10235-2-git-send-email-benoit.canet@gmail.com> In-Reply-To: <1320858224-10235-1-git-send-email-benoit.canet@gmail.com> References: <1320858224-10235-1-git-send-email-benoit.canet@gmail.com> Subject: [Qemu-devel] [PATCH 1/2] arm-linux-user: fix elfload.c's AT_HWCAP to reflect cpu features. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, =?UTF-8?q?Beno=C3=AEt=20Canet?= , afaerber@suse.de The cpu capabilities passed by the elf loader in AT_HWCAP were a constant. Make AT_HWCAP reflect the emulated cpu features in order to give correct clues to eglibc. Fix : [Bug 887516] [NEW] VFP support reported for the PXA270 Signed-off-by: Benoit Canet --- linux-user/elfload.c | 46 ++++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 42 insertions(+), 4 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index a413976..1c30c23 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -330,6 +330,10 @@ enum ARM_HWCAP_ARM_NEON = 1 << 11, ARM_HWCAP_ARM_VFPv3 = 1 << 12, ARM_HWCAP_ARM_VFPv3D16 = 1 << 13, + ARM_HWCAP_ARM_TLS = 1 << 14, + ARM_HWCAP_ARM_VFPv4 = 1 << 15, + ARM_HWCAP_ARM_IDIVA = 1 << 16, + ARM_HWCAP_ARM_IDIVT = 1 << 17, }; #define TARGET_HAS_GUEST_VALIDATE_BASE @@ -375,10 +379,44 @@ bool guest_validate_base(unsigned long guest_base) return 1; /* All good */ } -#define ELF_HWCAP (ARM_HWCAP_ARM_SWP | ARM_HWCAP_ARM_HALF \ - | ARM_HWCAP_ARM_THUMB | ARM_HWCAP_ARM_FAST_MULT \ - | ARM_HWCAP_ARM_FPA | ARM_HWCAP_ARM_VFP \ - | ARM_HWCAP_ARM_NEON | ARM_HWCAP_ARM_VFPv3 ) + +#define ELF_HWCAP get_elf_hwcap() + +static uint32_t get_elf_hwcap(void) +{ + CPUState *e = thread_env; + uint32_t hwcaps = 0; + + hwcaps |= ARM_HWCAP_ARM_SWP; + hwcaps |= ARM_HWCAP_ARM_HALF; + hwcaps |= ARM_HWCAP_ARM_THUMB; + hwcaps |= ARM_HWCAP_ARM_FAST_MULT; + + /* probe for the extra features */ +#define SET_HWCAP(feat, hwcap) do { \ + if (arm_feature(e, feat)) { \ + hwcaps |= hwcap; \ + } \ + } while (0) + SET_HWCAP(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); + SET_HWCAP(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); + SET_HWCAP(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); + SET_HWCAP(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); + SET_HWCAP(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); + + /* Strictly should be ARM_FEATURE_V5TE but we don't distinguish + * as all our v5 cores are v5TE at the moment + */ + SET_HWCAP(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); + + SET_HWCAP(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); + SET_HWCAP(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); + SET_HWCAP(ARM_FEATURE_ARM_DIV, ARM_HWCAP_ARM_IDIVA); + SET_HWCAP(ARM_FEATURE_THUMB_DIV, ARM_HWCAP_ARM_IDIVT); +#undef SET_HWCAP + + return hwcaps; +} #endif -- 1.7.5.4