From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: Stefan Weil <sw@weilnetz.de>, Alexander Graf <agraf@suse.de>,
Blue Swirl <blauwirbel@gmail.com>,
Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH 1/3] tcg: Standardize on TCGReg as the enum for hard registers
Date: Wed, 9 Nov 2011 10:03:33 -0800 [thread overview]
Message-ID: <1320861815-14317-2-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1320861815-14317-1-git-send-email-rth@twiddle.net>
Most targets did not name the enum; tci used TCGRegister.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/arm/tcg-target.h | 4 ++--
tcg/hppa/tcg-target.h | 4 ++--
tcg/i386/tcg-target.h | 4 ++--
tcg/ia64/tcg-target.h | 4 ++--
tcg/mips/tcg-target.h | 4 ++--
tcg/ppc/tcg-target.h | 4 ++--
tcg/ppc64/tcg-target.h | 4 ++--
tcg/sparc/tcg-target.h | 4 ++--
tcg/tci/tcg-target.h | 2 +-
tci.c | 38 +++++++++++++++++++-------------------
10 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 33afd97..48586c3 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -27,7 +27,7 @@
#undef TCG_TARGET_WORDS_BIGENDIAN
#undef TCG_TARGET_STACK_GROWSUP
-enum {
+typedef enum {
TCG_REG_R0 = 0,
TCG_REG_R1,
TCG_REG_R2,
@@ -44,7 +44,7 @@ enum {
TCG_REG_R13,
TCG_REG_R14,
TCG_REG_PC,
-};
+} TCGReg;
#define TCG_TARGET_NB_REGS 16
diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h
index ec9a7bf..7f3c4cc 100644
--- a/tcg/hppa/tcg-target.h
+++ b/tcg/hppa/tcg-target.h
@@ -32,7 +32,7 @@
#define TCG_TARGET_NB_REGS 32
-enum {
+typedef enum {
TCG_REG_R0 = 0,
TCG_REG_R1,
TCG_REG_RP,
@@ -65,7 +65,7 @@ enum {
TCG_REG_RET1,
TCG_REG_SP,
TCG_REG_R31,
-};
+} TCGReg;
#define TCG_CT_CONST_0 0x0100
#define TCG_CT_CONST_S5 0x0200
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index b9c9d4e..7756e7b 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -36,7 +36,7 @@
# define TCG_TARGET_NB_REGS 8
#endif
-enum {
+typedef enum {
TCG_REG_EAX = 0,
TCG_REG_ECX,
TCG_REG_EDX,
@@ -64,7 +64,7 @@ enum {
TCG_REG_RBP = TCG_REG_EBP,
TCG_REG_RSI = TCG_REG_ESI,
TCG_REG_RDI = TCG_REG_EDI,
-};
+} TCGReg;
#define TCG_CT_CONST_S32 0x100
#define TCG_CT_CONST_U32 0x200
diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
index 578cf29..c388089 100644
--- a/tcg/ia64/tcg-target.h
+++ b/tcg/ia64/tcg-target.h
@@ -26,7 +26,7 @@
/* We only map the first 64 registers */
#define TCG_TARGET_NB_REGS 64
-enum {
+typedef enum {
TCG_REG_R0 = 0,
TCG_REG_R1,
TCG_REG_R2,
@@ -91,7 +91,7 @@ enum {
TCG_REG_R61,
TCG_REG_R62,
TCG_REG_R63,
-};
+} TCGReg;
#define TCG_CT_CONST_ZERO 0x100
#define TCG_CT_CONST_S22 0x200
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index e2a2571..477bc38 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -31,7 +31,7 @@
#define TCG_TARGET_NB_REGS 32
-enum {
+typedef enum {
TCG_REG_ZERO = 0,
TCG_REG_AT,
TCG_REG_V0,
@@ -64,7 +64,7 @@ enum {
TCG_REG_SP,
TCG_REG_FP,
TCG_REG_RA,
-};
+} TCGReg;
#define TCG_CT_CONST_ZERO 0x100
#define TCG_CT_CONST_U16 0x200
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 25a6ea4..3f22aaa 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -26,7 +26,7 @@
#define TCG_TARGET_WORDS_BIGENDIAN
#define TCG_TARGET_NB_REGS 32
-enum {
+typedef enum {
TCG_REG_R0 = 0,
TCG_REG_R1,
TCG_REG_R2,
@@ -59,7 +59,7 @@ enum {
TCG_REG_R29,
TCG_REG_R30,
TCG_REG_R31
-};
+} TCGReg;
/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_R1
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index 8d1fb73..97eec08 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -26,7 +26,7 @@
#define TCG_TARGET_WORDS_BIGENDIAN
#define TCG_TARGET_NB_REGS 32
-enum {
+typedef enum {
TCG_REG_R0 = 0,
TCG_REG_R1,
TCG_REG_R2,
@@ -59,7 +59,7 @@ enum {
TCG_REG_R29,
TCG_REG_R30,
TCG_REG_R31
-};
+} TCGReg;
/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_R1
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 1464ef4..c3fe131 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -27,7 +27,7 @@
#define TCG_TARGET_NB_REGS 32
-enum {
+typedef enum {
TCG_REG_G0 = 0,
TCG_REG_G1,
TCG_REG_G2,
@@ -60,7 +60,7 @@ enum {
TCG_REG_I5,
TCG_REG_I6,
TCG_REG_I7,
-};
+} TCGReg;
#define TCG_CT_CONST_S11 0x100
#define TCG_CT_CONST_S13 0x200
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 81ded86..cb5858c 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -150,7 +150,7 @@ typedef enum {
#endif
/* Special value UINT8_MAX is used by TCI to encode constant values. */
TCG_CONST = UINT8_MAX
-} TCGRegister;
+} TCGReg;
void tci_disas(uint8_t opc);
diff --git a/tci.c b/tci.c
index f17785d..a20a714 100644
--- a/tci.c
+++ b/tci.c
@@ -63,90 +63,90 @@ void *tci_tb_ptr;
static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS];
-static tcg_target_ulong tci_read_reg(TCGRegister index)
+static tcg_target_ulong tci_read_reg(TCGReg index)
{
assert(index < ARRAY_SIZE(tci_reg));
return tci_reg[index];
}
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
-static int8_t tci_read_reg8s(TCGRegister index)
+static int8_t tci_read_reg8s(TCGReg index)
{
return (int8_t)tci_read_reg(index);
}
#endif
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
-static int16_t tci_read_reg16s(TCGRegister index)
+static int16_t tci_read_reg16s(TCGReg index)
{
return (int16_t)tci_read_reg(index);
}
#endif
#if TCG_TARGET_REG_BITS == 64
-static int32_t tci_read_reg32s(TCGRegister index)
+static int32_t tci_read_reg32s(TCGReg index)
{
return (int32_t)tci_read_reg(index);
}
#endif
-static uint8_t tci_read_reg8(TCGRegister index)
+static uint8_t tci_read_reg8(TCGReg index)
{
return (uint8_t)tci_read_reg(index);
}
-static uint16_t tci_read_reg16(TCGRegister index)
+static uint16_t tci_read_reg16(TCGReg index)
{
return (uint16_t)tci_read_reg(index);
}
-static uint32_t tci_read_reg32(TCGRegister index)
+static uint32_t tci_read_reg32(TCGReg index)
{
return (uint32_t)tci_read_reg(index);
}
#if TCG_TARGET_REG_BITS == 64
-static uint64_t tci_read_reg64(TCGRegister index)
+static uint64_t tci_read_reg64(TCGReg index)
{
return tci_read_reg(index);
}
#endif
-static void tci_write_reg(TCGRegister index, tcg_target_ulong value)
+static void tci_write_reg(TCGReg index, tcg_target_ulong value)
{
assert(index < ARRAY_SIZE(tci_reg));
assert(index != TCG_AREG0);
tci_reg[index] = value;
}
-static void tci_write_reg8s(TCGRegister index, int8_t value)
+static void tci_write_reg8s(TCGReg index, int8_t value)
{
tci_write_reg(index, value);
}
-static void tci_write_reg16s(TCGRegister index, int16_t value)
+static void tci_write_reg16s(TCGReg index, int16_t value)
{
tci_write_reg(index, value);
}
#if TCG_TARGET_REG_BITS == 64
-static void tci_write_reg32s(TCGRegister index, int32_t value)
+static void tci_write_reg32s(TCGReg index, int32_t value)
{
tci_write_reg(index, value);
}
#endif
-static void tci_write_reg8(TCGRegister index, uint8_t value)
+static void tci_write_reg8(TCGReg index, uint8_t value)
{
tci_write_reg(index, value);
}
-static void tci_write_reg16(TCGRegister index, uint16_t value)
+static void tci_write_reg16(TCGReg index, uint16_t value)
{
tci_write_reg(index, value);
}
-static void tci_write_reg32(TCGRegister index, uint32_t value)
+static void tci_write_reg32(TCGReg index, uint32_t value)
{
tci_write_reg(index, value);
}
@@ -159,7 +159,7 @@ static void tci_write_reg64(uint32_t high_index, uint32_t low_index,
tci_write_reg(high_index, value >> 32);
}
#elif TCG_TARGET_REG_BITS == 64
-static void tci_write_reg64(TCGRegister index, uint64_t value)
+static void tci_write_reg64(TCGReg index, uint64_t value)
{
tci_write_reg(index, value);
}
@@ -290,7 +290,7 @@ static target_ulong tci_read_ulong(uint8_t **tb_ptr)
static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr)
{
tcg_target_ulong value;
- TCGRegister r = **tb_ptr;
+ TCGReg r = **tb_ptr;
*tb_ptr += 1;
if (r == TCG_CONST) {
value = tci_read_i(tb_ptr);
@@ -304,7 +304,7 @@ static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr)
static uint32_t tci_read_ri32(uint8_t **tb_ptr)
{
uint32_t value;
- TCGRegister r = **tb_ptr;
+ TCGReg r = **tb_ptr;
*tb_ptr += 1;
if (r == TCG_CONST) {
value = tci_read_i32(tb_ptr);
@@ -326,7 +326,7 @@ static uint64_t tci_read_ri64(uint8_t **tb_ptr)
static uint64_t tci_read_ri64(uint8_t **tb_ptr)
{
uint64_t value;
- TCGRegister r = **tb_ptr;
+ TCGReg r = **tb_ptr;
*tb_ptr += 1;
if (r == TCG_CONST) {
value = tci_read_i64(tb_ptr);
--
1.7.6.4
next prev parent reply other threads:[~2011-11-09 18:04 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-11-09 18:03 [Qemu-devel] [PATCH 0/3] Standardize on TCGReg for entry points Richard Henderson
2011-11-09 18:03 ` Richard Henderson [this message]
2011-11-09 18:03 ` [Qemu-devel] [PATCH 2/3] tcg: Use TCGReg for standard tcg-target " Richard Henderson
2011-11-09 18:03 ` [Qemu-devel] [PATCH 3/3] tcg-sparc: Fix set-but-not used warnings Richard Henderson
2011-11-19 13:59 ` Blue Swirl
2011-11-09 18:51 ` [Qemu-devel] [PATCH 0/3] Standardize on TCGReg for entry points Andreas Färber
2011-11-09 20:19 ` Stefan Weil
2011-11-09 22:11 ` Richard Henderson
2011-11-10 13:40 ` Alexander Graf
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