From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:33215) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RORvb-0005RE-8X for qemu-devel@nongnu.org; Thu, 10 Nov 2011 05:32:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RORvZ-0007l6-Pk for qemu-devel@nongnu.org; Thu, 10 Nov 2011 05:32:15 -0500 Received: from fmmailgate05.web.de ([217.72.192.243]:57766) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RORvZ-0007ke-Du for qemu-devel@nongnu.org; Thu, 10 Nov 2011 05:32:13 -0500 Received: from moweb001.kundenserver.de (moweb001.kundenserver.de [172.19.20.114]) by fmmailgate05.web.de (Postfix) with ESMTP id C07A7677C643 for ; Thu, 10 Nov 2011 11:32:12 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 10 Nov 2011 11:31:59 +0100 Message-Id: <1320921120-11574-5-git-send-email-andreas.faerber@web.de> In-Reply-To: <1320921120-11574-1-git-send-email-andreas.faerber@web.de> References: <1319281250-27114-1-git-send-email-andreas.faerber@web.de> <1320921120-11574-1-git-send-email-andreas.faerber@web.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [FYI 4/5] target-arm: Prepare support for Cortex-R4 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= Glue "cortex-r4" to r1p4, the latest available TRM. Set MPU and Thumb division feature bit. Cc: Peter Maydell Signed-off-by: Andreas F=C3=A4rber --- target-arm/cpu.h | 1 + target-arm/helper.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 0 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index c38dfd5..44868e6 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -427,6 +427,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define ARM_CPUID_ARM11MPCORE 0x410fb022 #define ARM_CPUID_CORTEXA8 0x410fc080 #define ARM_CPUID_CORTEXA9 0x410fc090 +#define ARM_CPUID_CORTEXR4_R1P4 0x411FC144 #define ARM_CPUID_CORTEXM3 0x410fc231 #define ARM_CPUID_ANY 0xffffffff =20 diff --git a/target-arm/helper.c b/target-arm/helper.c index 3de0781..4836762 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -41,6 +41,12 @@ static uint32_t arm1176_cp15_c0_c1[8] =3D static uint32_t arm1176_cp15_c0_c2[8] =3D { 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 }; =20 +static uint32_t cortexr4_cp15_c0_c1[8] =3D +{ 0x0131, 0x001, 0x010400, 0x0, 0x0210030, 0x00000000, 0x01200000, 0x021= 1 }; + +static uint32_t cortexr4_cp15_c0_c2[8] =3D +{ 0x1101111, 0x13112111, 0x21232131, 0x01112131, 0x0010142, 0x0, 0, 0 }; + static uint32_t cpu_arm_find_by_name(const char *name); =20 static inline void set_feature(CPUARMState *env, int feature) @@ -170,6 +176,14 @@ static void cpu_reset_model_id(CPUARMState *env) env->cp15.c0_ccsid[1] =3D 0x200fe015; /* 16k L1 icache. */ env->cp15.c1_sys =3D 0x00c50078; break; + case ARM_CPUID_CORTEXR4_R1P4: + set_feature(env, ARM_FEATURE_V7); + set_feature(env, ARM_FEATURE_THUMB2); + set_feature(env, ARM_FEATURE_THUMB_DIV); + set_feature(env, ARM_FEATURE_MPU); + memcpy(env->cp15.c0_c1, cortexr4_cp15_c0_c1, 8 * sizeof(uint32_t= )); + memcpy(env->cp15.c0_c2, cortexr4_cp15_c0_c2, 8 * sizeof(uint32_t= )); + break; case ARM_CPUID_CORTEXM3: set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_V7); @@ -408,6 +422,7 @@ static const struct arm_cpu_t arm_cpu_names[] =3D { { ARM_CPUID_CORTEXM3, "cortex-m3"}, { ARM_CPUID_CORTEXA8, "cortex-a8"}, { ARM_CPUID_CORTEXA9, "cortex-a9"}, + { ARM_CPUID_CORTEXR4_R1P4, "cortex-r4"}, { ARM_CPUID_TI925T, "ti925t" }, { ARM_CPUID_PXA250, "pxa250" }, { ARM_CPUID_SA1100, "sa1100" }, --=20 1.7.7