From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:33224) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RORvb-0005RG-N5 for qemu-devel@nongnu.org; Thu, 10 Nov 2011 05:32:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RORva-0007lJ-6Y for qemu-devel@nongnu.org; Thu, 10 Nov 2011 05:32:15 -0500 Received: from fmmailgate04.web.de ([217.72.192.242]:40507) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RORvZ-0007l1-P7 for qemu-devel@nongnu.org; Thu, 10 Nov 2011 05:32:14 -0500 Received: from moweb002.kundenserver.de (moweb002.kundenserver.de [172.19.20.108]) by fmmailgate04.web.de (Postfix) with ESMTP id 281AD6EEAC65 for ; Thu, 10 Nov 2011 11:32:13 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 10 Nov 2011 11:32:00 +0100 Message-Id: <1320921120-11574-6-git-send-email-andreas.faerber@web.de> In-Reply-To: <1320921120-11574-1-git-send-email-andreas.faerber@web.de> References: <1319281250-27114-1-git-send-email-andreas.faerber@web.de> <1320921120-11574-1-git-send-email-andreas.faerber@web.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [FYI 5/5] target-arm: Add support for Cortex-R4F List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= Since no clean distinction between R4 and R4F can be made yet, default -cpu cortex-r4 to Cortex-R4F. Cc: Peter Maydell Signed-off-by: Andreas F=C3=A4rber --- target-arm/helper.c | 34 ++++++++++++++++++++++++++++++++++ 1 files changed, 34 insertions(+), 0 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 4836762..15853e0 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -181,6 +181,40 @@ static void cpu_reset_model_id(CPUARMState *env) set_feature(env, ARM_FEATURE_THUMB2); set_feature(env, ARM_FEATURE_THUMB_DIV); set_feature(env, ARM_FEATURE_MPU); + { + static const struct { + uint8_t r; + uint8_t p; + uint8_t value; + } fpsid_revs[] =3D { + { 1, 0, 0x3 }, + { 1, 1, 0x4 }, + { 1, 2, 0x6 }, + { 1, 3, 0x7 }, + { 1, 4, 0x8 }, + {} + }; + uint8_t r =3D (ARM_CPUID(env) >> 20) & 0xf; + uint8_t p =3D ARM_CPUID(env) & 0xf; + uint8_t rev =3D 0; + int i; + set_feature(env, ARM_FEATURE_VFP); + set_feature(env, ARM_FEATURE_VFP3); + /* TODO VFPv3-D16 */ + /* Calculate FPSID value matching to MIDR */ + for (i =3D 0; fpsid_revs[i].r !=3D 0; i++) { + if (fpsid_revs[i].r =3D=3D r && fpsid_revs[i].p =3D=3D p= ) { + rev =3D fpsid_revs[i].value; + break; + } + } + if (rev =3D=3D 0) { + cpu_abort(env, + "Cortex-R4F r%" PRIu8 "p%" PRIu8 " unsupported= ", + r, p); + } + env->vfp.xregs[ARM_VFP_FPSID] =3D 0x41023140 | (rev & 0xf); + } memcpy(env->cp15.c0_c1, cortexr4_cp15_c0_c1, 8 * sizeof(uint32_t= )); memcpy(env->cp15.c0_c2, cortexr4_cp15_c0_c2, 8 * sizeof(uint32_t= )); break; --=20 1.7.7