From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:43549) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RPata-00037n-Cr for qemu-devel@nongnu.org; Sun, 13 Nov 2011 09:18:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RPatZ-0006FM-67 for qemu-devel@nongnu.org; Sun, 13 Nov 2011 09:18:54 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:40303) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RPatY-0006FF-VY for qemu-devel@nongnu.org; Sun, 13 Nov 2011 09:18:53 -0500 From: Peter Maydell Date: Sun, 13 Nov 2011 14:18:39 +0000 Message-Id: <1321193919-17148-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH] hw/pxa2xx.c: Fix handling of RW bits in PMCR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Anthony Liguori , patches@linaro.org Fix an error in commit afd4a6522 which meant that writing a zero to the RW bits in the PMCR wouldn't actually clear them. (Error spotted by Andrzej Zaborowski.) Signed-off-by: Peter Maydell --- This fixes the bug Andrzej pointed out in comments on the earlier patch; sorry about this error. I opted to use a separate & rather than merging the bit-clearing in with the W1C handling for clarity. hw/pxa2xx.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index d38b922..e9a507e 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -117,6 +117,7 @@ static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr, /* Clear the write-one-to-clear bits... */ s->pm_regs[addr >> 2] &= ~(value & 0x2a); /* ...and set the plain r/w bits */ + s->pm_regs[addr >> 2] &= ~0x15; s->pm_regs[addr >> 2] |= value & 0x15; break; -- 1.7.4.1