* [Qemu-devel] [PATCH 1/5] sh7750: convert memory controller/ioport to memory API
2011-11-17 12:24 [Qemu-devel] [PATCH 0/5] Convert remaining sh4 devices to memory API Benoît Canet
@ 2011-11-17 12:24 ` Benoît Canet
2011-11-17 12:46 ` Avi Kivity
2011-11-17 12:24 ` [Qemu-devel] [PATCH 2/5] sh7750: convert cache and tlb " Benoît Canet
` (3 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Benoît Canet @ 2011-11-17 12:24 UTC (permalink / raw)
To: qemu-devel; +Cc: Benoît Canet, avi
Signed-off-by: Benoit Canet <benoit.canet@gmail.com>
---
hw/r2d.c | 2 +-
hw/sh.h | 3 +-
hw/sh7750.c | 72 ++++++++++++++++++++++++++++++++++++----------------------
hw/shix.c | 2 +-
4 files changed, 49 insertions(+), 30 deletions(-)
diff --git a/hw/r2d.c b/hw/r2d.c
index a9aefa2..9b6fcba 100644
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -250,7 +250,7 @@ static void r2d_init(ram_addr_t ram_size,
memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE);
memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
/* Register peripherals */
- s = sh7750_init(env);
+ s = sh7750_init(env, address_space_mem);
irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
sysbus_create_varargs("sh_pci", 0x1e200000, irq[PCI_INTA], irq[PCI_INTB],
irq[PCI_INTC], irq[PCI_INTD], NULL);
diff --git a/hw/sh.h b/hw/sh.h
index d30e9f5..cf3f6f6 100644
--- a/hw/sh.h
+++ b/hw/sh.h
@@ -9,8 +9,9 @@
/* sh7750.c */
struct SH7750State;
+struct MemoryRegion;
-struct SH7750State *sh7750_init(CPUState * cpu);
+struct SH7750State *sh7750_init(CPUState * cpu, struct MemoryRegion *sysmem);
typedef struct {
/* The callback will be triggered if any of the designated lines change */
diff --git a/hw/sh7750.c b/hw/sh7750.c
index 9f3ea92..5cee76a 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -30,10 +30,18 @@
#include "sh7750_regnames.h"
#include "sh_intc.h"
#include "cpu.h"
+#include "exec-memory.h"
#define NB_DEVICES 4
typedef struct SH7750State {
+ MemoryRegion iomem;
+ MemoryRegion iomem_1f0;
+ MemoryRegion iomem_ff0;
+ MemoryRegion iomem_1f8;
+ MemoryRegion iomem_ff8;
+ MemoryRegion iomem_1fc;
+ MemoryRegion iomem_ffc;
/* CPU */
CPUSH4State *cpu;
/* Peripheral frequency in Hz */
@@ -436,16 +444,16 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const sh7750_mem_read[] = {
- sh7750_mem_readb,
- sh7750_mem_readw,
- sh7750_mem_readl
-};
-
-static CPUWriteMemoryFunc * const sh7750_mem_write[] = {
- sh7750_mem_writeb,
- sh7750_mem_writew,
- sh7750_mem_writel
+static const MemoryRegionOps sh7750_mem_ops = {
+ .old_mmio = {
+ .read = {sh7750_mem_readb,
+ sh7750_mem_readw,
+ sh7750_mem_readl },
+ .write = {sh7750_mem_writeb,
+ sh7750_mem_writew,
+ sh7750_mem_writel },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
/* sh775x interrupt controller tables for sh_intc.c
@@ -706,30 +714,40 @@ static CPUWriteMemoryFunc * const sh7750_mmct_write[] = {
sh7750_mmct_writel
};
-SH7750State *sh7750_init(CPUSH4State * cpu)
+SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
{
SH7750State *s;
- int sh7750_io_memory;
int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */
s = g_malloc0(sizeof(SH7750State));
s->cpu = cpu;
s->periph_freq = 60000000; /* 60MHz */
- sh7750_io_memory = cpu_register_io_memory(sh7750_mem_read,
- sh7750_mem_write, s,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory_offset(0x1f000000, 0x1000,
- sh7750_io_memory, 0x1f000000);
- cpu_register_physical_memory_offset(0xff000000, 0x1000,
- sh7750_io_memory, 0x1f000000);
- cpu_register_physical_memory_offset(0x1f800000, 0x1000,
- sh7750_io_memory, 0x1f800000);
- cpu_register_physical_memory_offset(0xff800000, 0x1000,
- sh7750_io_memory, 0x1f800000);
- cpu_register_physical_memory_offset(0x1fc00000, 0x1000,
- sh7750_io_memory, 0x1fc00000);
- cpu_register_physical_memory_offset(0xffc00000, 0x1000,
- sh7750_io_memory, 0x1fc00000);
+ memory_region_init_io(&s->iomem, &sh7750_mem_ops, s,
+ "memory", 0x1fe00000);
+
+ memory_region_init_alias(&s->iomem_1f0, "memory-1f0",
+ &s->iomem, 0x1f000000, 0x1000);
+ memory_region_add_subregion(sysmem, 0x1f000000, &s->iomem_1f0);
+
+ memory_region_init_alias(&s->iomem_ff0, "memory-ff0",
+ &s->iomem, 0x1f000000, 0x1000);
+ memory_region_add_subregion(sysmem, 0xff000000, &s->iomem_ff0);
+
+ memory_region_init_alias(&s->iomem_1f8, "memory-1f8",
+ &s->iomem, 0x1f800000, 0x1000);
+ memory_region_add_subregion(sysmem, 0x1f800000, &s->iomem_1f8);
+
+ memory_region_init_alias(&s->iomem_ff8, "memory-ff8",
+ &s->iomem, 0x1f800000, 0x1000);
+ memory_region_add_subregion(sysmem, 0xff800000, &s->iomem_ff8);
+
+ memory_region_init_alias(&s->iomem_1fc, "memory-1fc",
+ &s->iomem, 0x1fc00000, 0x1000);
+ memory_region_add_subregion(sysmem, 0x1fc00000, &s->iomem_1fc);
+
+ memory_region_init_alias(&s->iomem_ffc, "memory-ffc",
+ &s->iomem, 0x1fc00000, 0x1000);
+ memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc);
sh7750_mm_cache_and_tlb = cpu_register_io_memory(sh7750_mmct_read,
sh7750_mmct_write, s,
diff --git a/hw/shix.c b/hw/shix.c
index 670ddb5..e0c2200 100644
--- a/hw/shix.c
+++ b/hw/shix.c
@@ -80,7 +80,7 @@ static void shix_init(ram_addr_t ram_size,
}
/* Register peripherals */
- s = sh7750_init(env);
+ s = sh7750_init(env, sysmem);
/* XXXXX Check success */
tc58128_init(s, "shix_linux_nand.bin", NULL);
fprintf(stderr, "initialization terminated\n");
--
1.7.5.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [Qemu-devel] [PATCH 1/5] sh7750: convert memory controller/ioport to memory API
2011-11-17 12:24 ` [Qemu-devel] [PATCH 1/5] sh7750: convert memory controller/ioport " Benoît Canet
@ 2011-11-17 12:46 ` Avi Kivity
0 siblings, 0 replies; 10+ messages in thread
From: Avi Kivity @ 2011-11-17 12:46 UTC (permalink / raw)
To: Benoît Canet; +Cc: qemu-devel
On 11/17/2011 02:24 PM, Benoît Canet wrote:
> Signed-off-by: Benoit Canet <benoit.canet@gmail.com>
>
> /* sh775x interrupt controller tables for sh_intc.c
> @@ -706,30 +714,40 @@ static CPUWriteMemoryFunc * const sh7750_mmct_write[] = {
> sh7750_mmct_writel
> };
>
> -SH7750State *sh7750_init(CPUSH4State * cpu)
> +SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
> {
> SH7750State *s;
> - int sh7750_io_memory;
> int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */
>
> s = g_malloc0(sizeof(SH7750State));
> s->cpu = cpu;
> s->periph_freq = 60000000; /* 60MHz */
> - sh7750_io_memory = cpu_register_io_memory(sh7750_mem_read,
> - sh7750_mem_write, s,
> - DEVICE_NATIVE_ENDIAN);
> - cpu_register_physical_memory_offset(0x1f000000, 0x1000,
> - sh7750_io_memory, 0x1f000000);
> - cpu_register_physical_memory_offset(0xff000000, 0x1000,
> - sh7750_io_memory, 0x1f000000);
> - cpu_register_physical_memory_offset(0x1f800000, 0x1000,
> - sh7750_io_memory, 0x1f800000);
> - cpu_register_physical_memory_offset(0xff800000, 0x1000,
> - sh7750_io_memory, 0x1f800000);
> - cpu_register_physical_memory_offset(0x1fc00000, 0x1000,
> - sh7750_io_memory, 0x1fc00000);
> - cpu_register_physical_memory_offset(0xffc00000, 0x1000,
> - sh7750_io_memory, 0x1fc00000);
> + memory_region_init_io(&s->iomem, &sh7750_mem_ops, s,
> + "memory", 0x1fe00000);
Any size >= 0x1fc01000 will work here, why did you pick px1fe00000?
just curious.
I see serial starts at that address, but note that even a larger size
won't interfere, since we never add anything to sysmem at that address.
Anyway, no need to change the patch, since it will work just fine.
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Qemu-devel] [PATCH 2/5] sh7750: convert cache and tlb to memory API
2011-11-17 12:24 [Qemu-devel] [PATCH 0/5] Convert remaining sh4 devices to memory API Benoît Canet
2011-11-17 12:24 ` [Qemu-devel] [PATCH 1/5] sh7750: convert memory controller/ioport " Benoît Canet
@ 2011-11-17 12:24 ` Benoît Canet
2011-11-17 12:24 ` [Qemu-devel] [PATCH 3/5] sh_timer: convert " Benoît Canet
` (2 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Benoît Canet @ 2011-11-17 12:24 UTC (permalink / raw)
To: qemu-devel; +Cc: Benoît Canet, avi
Signed-off-by: Benoit Canet <benoit.canet@gmail.com>
---
hw/sh7750.c | 43 ++++++++++++++++++++++---------------------
1 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/hw/sh7750.c b/hw/sh7750.c
index 5cee76a..fd48c4a 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -42,6 +42,7 @@ typedef struct SH7750State {
MemoryRegion iomem_ff8;
MemoryRegion iomem_1fc;
MemoryRegion iomem_ffc;
+ MemoryRegion mmct_iomem;
/* CPU */
CPUSH4State *cpu;
/* Peripheral frequency in Hz */
@@ -623,18 +624,23 @@ static struct intc_group groups_irl[] = {
#define MM_UTLB_DATA (7)
#define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24)
-static uint32_t invalid_read(void *opaque, target_phys_addr_t addr)
+static uint64_t invalid_read(void *opaque, target_phys_addr_t addr)
{
abort();
return 0;
}
-static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t sh7750_mmct_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
SH7750State *s = opaque;
uint32_t ret = 0;
+ if (size != 4) {
+ return invalid_read(opaque, addr);
+ }
+
switch (MM_REGION_TYPE(addr)) {
case MM_ICACHE_ADDR:
case MM_ICACHE_DATA:
@@ -664,16 +670,20 @@ static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
}
static void invalid_write(void *opaque, target_phys_addr_t addr,
- uint32_t mem_value)
+ uint64_t mem_value)
{
abort();
}
-static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
- uint32_t mem_value)
+static void sh7750_mmct_write(void *opaque, target_phys_addr_t addr,
+ uint64_t mem_value, unsigned size)
{
SH7750State *s = opaque;
+ if (size != 4) {
+ invalid_write(opaque, addr, mem_value);
+ }
+
switch (MM_REGION_TYPE(addr)) {
case MM_ICACHE_ADDR:
case MM_ICACHE_DATA:
@@ -702,22 +712,15 @@ static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc * const sh7750_mmct_read[] = {
- invalid_read,
- invalid_read,
- sh7750_mmct_readl
-};
-
-static CPUWriteMemoryFunc * const sh7750_mmct_write[] = {
- invalid_write,
- invalid_write,
- sh7750_mmct_writel
+static const struct MemoryRegionOps sh7750_mmct_ops = {
+ .read = sh7750_mmct_read,
+ .write = sh7750_mmct_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
{
SH7750State *s;
- int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */
s = g_malloc0(sizeof(SH7750State));
s->cpu = cpu;
@@ -749,11 +752,9 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
&s->iomem, 0x1fc00000, 0x1000);
memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc);
- sh7750_mm_cache_and_tlb = cpu_register_io_memory(sh7750_mmct_read,
- sh7750_mmct_write, s,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(0xf0000000, 0x08000000,
- sh7750_mm_cache_and_tlb);
+ memory_region_init_io(&s->mmct_iomem, &sh7750_mmct_ops, s,
+ "cache-and-tlb", 0x08000000);
+ memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem);
sh_intc_init(&s->intc, NR_SOURCES,
_INTC_ARRAY(mask_registers),
--
1.7.5.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Qemu-devel] [PATCH 3/5] sh_timer: convert to memory API
2011-11-17 12:24 [Qemu-devel] [PATCH 0/5] Convert remaining sh4 devices to memory API Benoît Canet
2011-11-17 12:24 ` [Qemu-devel] [PATCH 1/5] sh7750: convert memory controller/ioport " Benoît Canet
2011-11-17 12:24 ` [Qemu-devel] [PATCH 2/5] sh7750: convert cache and tlb " Benoît Canet
@ 2011-11-17 12:24 ` Benoît Canet
2011-11-17 12:24 ` [Qemu-devel] [PATCH 4/5] sh_intc: convert interrupt controller " Benoît Canet
2011-11-17 12:25 ` [Qemu-devel] [PATCH 5/5] sh_serial: convert " Benoît Canet
4 siblings, 0 replies; 10+ messages in thread
From: Benoît Canet @ 2011-11-17 12:24 UTC (permalink / raw)
To: qemu-devel; +Cc: Benoît Canet, avi
Signed-off-by: Benoit Canet <benoit.canet@gmail.com>
---
hw/sh.h | 3 ++-
hw/sh7750.c | 4 ++--
hw/sh_timer.c | 43 ++++++++++++++++++++++++-------------------
3 files changed, 28 insertions(+), 22 deletions(-)
diff --git a/hw/sh.h b/hw/sh.h
index cf3f6f6..c764be6 100644
--- a/hw/sh.h
+++ b/hw/sh.h
@@ -31,7 +31,8 @@ int sh7750_register_io_device(struct SH7750State *s,
#define TMU012_FEAT_TOCR (1 << 0)
#define TMU012_FEAT_3CHAN (1 << 1)
#define TMU012_FEAT_EXTCLK (1 << 2)
-void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
+void tmu012_init(struct MemoryRegion *sysmem, target_phys_addr_t base,
+ int feat, uint32_t freq,
qemu_irq ch0_irq, qemu_irq ch1_irq,
qemu_irq ch2_irq0, qemu_irq ch2_irq1);
diff --git a/hw/sh7750.c b/hw/sh7750.c
index fd48c4a..e181305 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -780,7 +780,7 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
NULL,
s->intc.irqs[SCIF_BRI]);
- tmu012_init(0x1fd80000,
+ tmu012_init(sysmem, 0x1fd80000,
TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
s->periph_freq,
s->intc.irqs[TMU0],
@@ -804,7 +804,7 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_tmu34),
NULL, 0);
- tmu012_init(0x1e100000, 0, s->periph_freq,
+ tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq,
s->intc.irqs[TMU3],
s->intc.irqs[TMU4],
NULL, NULL);
diff --git a/hw/sh_timer.c b/hw/sh_timer.c
index dca3c94..9132207 100644
--- a/hw/sh_timer.c
+++ b/hw/sh_timer.c
@@ -11,6 +11,7 @@
#include "hw.h"
#include "sh.h"
#include "qemu-timer.h"
+#include "exec-memory.h"
//#define DEBUG_TIMER
@@ -210,6 +211,9 @@ static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
}
typedef struct {
+ MemoryRegion iomem;
+ MemoryRegion iomem_p4;
+ MemoryRegion iomem_a7;
void *timer[3];
int level[3];
uint32_t tocr;
@@ -217,7 +221,8 @@ typedef struct {
int feat;
} tmu012_state;
-static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset)
+static uint64_t tmu012_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
tmu012_state *s = (tmu012_state *)opaque;
@@ -248,7 +253,7 @@ static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset)
}
static void tmu012_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
tmu012_state *s = (tmu012_state *)opaque;
@@ -291,23 +296,17 @@ static void tmu012_write(void *opaque, target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc * const tmu012_readfn[] = {
- tmu012_read,
- tmu012_read,
- tmu012_read
+static const MemoryRegionOps tmu012_ops = {
+ .read = tmu012_read,
+ .write = tmu012_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const tmu012_writefn[] = {
- tmu012_write,
- tmu012_write,
- tmu012_write
-};
-
-void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
+void tmu012_init(MemoryRegion *sysmem, target_phys_addr_t base,
+ int feat, uint32_t freq,
qemu_irq ch0_irq, qemu_irq ch1_irq,
qemu_irq ch2_irq0, qemu_irq ch2_irq1)
{
- int iomemtype;
tmu012_state *s;
int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
@@ -318,10 +317,16 @@ void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
if (feat & TMU012_FEAT_3CHAN)
s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
ch2_irq0); /* ch2_irq1 not supported */
- iomemtype = cpu_register_io_memory(tmu012_readfn,
- tmu012_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(P4ADDR(base), 0x00001000, iomemtype);
- cpu_register_physical_memory(A7ADDR(base), 0x00001000, iomemtype);
+
+ memory_region_init_io(&s->iomem, &tmu012_ops, s,
+ "timer", 0x100000000ULL);
+
+ memory_region_init_alias(&s->iomem_p4, "timer-p4",
+ &s->iomem, 0, 0x1000);
+ memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
+
+ memory_region_init_alias(&s->iomem_a7, "timer-a7",
+ &s->iomem, 0, 0x1000);
+ memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
/* ??? Save/restore. */
}
--
1.7.5.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Qemu-devel] [PATCH 4/5] sh_intc: convert interrupt controller to memory API
2011-11-17 12:24 [Qemu-devel] [PATCH 0/5] Convert remaining sh4 devices to memory API Benoît Canet
` (2 preceding siblings ...)
2011-11-17 12:24 ` [Qemu-devel] [PATCH 3/5] sh_timer: convert " Benoît Canet
@ 2011-11-17 12:24 ` Benoît Canet
2011-11-17 12:56 ` Peter Maydell
2011-11-17 12:25 ` [Qemu-devel] [PATCH 5/5] sh_serial: convert " Benoît Canet
4 siblings, 1 reply; 10+ messages in thread
From: Benoît Canet @ 2011-11-17 12:24 UTC (permalink / raw)
To: qemu-devel; +Cc: Benoît Canet, avi
Signed-off-by: Benoit Canet <benoit.canet@gmail.com>
---
hw/sh7750.c | 2 +-
hw/sh_intc.c | 87 ++++++++++++++++++++++++++++++++++----------------
hw/sh_intc.h | 7 +++-
target-sh4/helper.c | 3 ++
4 files changed, 68 insertions(+), 31 deletions(-)
diff --git a/hw/sh7750.c b/hw/sh7750.c
index e181305..930d212 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -756,7 +756,7 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
"cache-and-tlb", 0x08000000);
memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem);
- sh_intc_init(&s->intc, NR_SOURCES,
+ sh_intc_init(sysmem, &s->intc, NR_SOURCES,
_INTC_ARRAY(mask_registers),
_INTC_ARRAY(prio_registers));
diff --git a/hw/sh_intc.c b/hw/sh_intc.c
index e07424f..38cefc9 100644
--- a/hw/sh_intc.c
+++ b/hw/sh_intc.c
@@ -219,7 +219,8 @@ static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
#endif
}
-static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset)
+static uint64_t sh_intc_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
struct intc_desc *desc = opaque;
intc_enum *enum_ids = NULL;
@@ -238,7 +239,7 @@ static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset)
}
static void sh_intc_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct intc_desc *desc = opaque;
intc_enum *enum_ids = NULL;
@@ -282,16 +283,10 @@ static void sh_intc_write(void *opaque, target_phys_addr_t offset,
#endif
}
-static CPUReadMemoryFunc * const sh_intc_readfn[] = {
- sh_intc_read,
- sh_intc_read,
- sh_intc_read
-};
-
-static CPUWriteMemoryFunc * const sh_intc_writefn[] = {
- sh_intc_write,
- sh_intc_write,
- sh_intc_write
+static const struct MemoryRegionOps sh_intc_ops = {
+ .read = sh_intc_read,
+ .write = sh_intc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
@@ -302,15 +297,36 @@ struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
return NULL;
}
-static void sh_intc_register(struct intc_desc *desc,
- unsigned long address)
+static unsigned int sh_intc_register(MemoryRegion *sysmem,
+ struct intc_desc *desc,
+ const unsigned long address,
+ const char *type,
+ const char *action,
+ const unsigned int index)
{
- if (address) {
- cpu_register_physical_memory_offset(P4ADDR(address), 4,
- desc->iomemtype, INTC_A7(address));
- cpu_register_physical_memory_offset(A7ADDR(address), 4,
- desc->iomemtype, INTC_A7(address));
+ char name[60];
+ MemoryRegion *iomem, *iomem_p4, *iomem_a7;
+
+ if (!address) {
+ return 0;
}
+
+ iomem = &desc->iomem;
+ iomem_p4 = desc->iomem_aliases + index;
+ iomem_a7 = iomem_p4 + 1;
+
+#define SH_INTC_IOMEM_FORMAT "interrupt-controller-%s-%s-%s"
+ snprintf(name, sizeof(name), SH_INTC_IOMEM_FORMAT, type, action, "p4");
+ memory_region_init_alias(iomem_p4, name, iomem, INTC_A7(address), 4);
+ memory_region_add_subregion(sysmem, P4ADDR(address), iomem_p4);
+
+ snprintf(name, sizeof(name), SH_INTC_IOMEM_FORMAT, type, action, "a7");
+ memory_region_init_alias(iomem_a7, name, iomem, INTC_A7(address), 4);
+ memory_region_add_subregion(sysmem, A7ADDR(address), iomem_a7);
+#undef SH_INTC_IOMEM_FORMAT
+
+ /* used to increment aliases index */
+ return 2;
}
static void sh_intc_register_source(struct intc_desc *desc,
@@ -415,14 +431,15 @@ void sh_intc_register_sources(struct intc_desc *desc,
}
}
-int sh_intc_init(struct intc_desc *desc,
+int sh_intc_init(MemoryRegion *sysmem,
+ struct intc_desc *desc,
int nr_sources,
struct intc_mask_reg *mask_regs,
int nr_mask_regs,
struct intc_prio_reg *prio_regs,
int nr_prio_regs)
{
- unsigned int i;
+ unsigned int i, j;
desc->pending = 0;
desc->nr_sources = nr_sources;
@@ -430,7 +447,11 @@ int sh_intc_init(struct intc_desc *desc,
desc->nr_mask_regs = nr_mask_regs;
desc->prio_regs = prio_regs;
desc->nr_prio_regs = nr_prio_regs;
+ /* Allocate 4 MemoryRegions per register (2 actions * 2 aliases). */
+ desc->iomem_aliases = g_new0(MemoryRegion,
+ (nr_mask_regs + nr_prio_regs) * 4);
+ j = 0;
i = sizeof(struct intc_source) * nr_sources;
desc->sources = g_malloc0(i);
@@ -442,15 +463,19 @@ int sh_intc_init(struct intc_desc *desc,
desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
- desc->iomemtype = cpu_register_io_memory(sh_intc_readfn,
- sh_intc_writefn, desc,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&desc->iomem, &sh_intc_ops, desc,
+ "interrupt-controller", 0x100000000ULL);
+
+#define INT_REG_PARAMS(reg_struct, type, action, j) \
+ reg_struct->action##_reg, #type, #action, j
if (desc->mask_regs) {
for (i = 0; i < desc->nr_mask_regs; i++) {
struct intc_mask_reg *mr = desc->mask_regs + i;
- sh_intc_register(desc, mr->set_reg);
- sh_intc_register(desc, mr->clr_reg);
+ j += sh_intc_register(sysmem, desc,
+ INT_REG_PARAMS(mr, mask, set, j));
+ j += sh_intc_register(sysmem, desc,
+ INT_REG_PARAMS(mr, mask, clr, j));
}
}
@@ -458,10 +483,16 @@ int sh_intc_init(struct intc_desc *desc,
for (i = 0; i < desc->nr_prio_regs; i++) {
struct intc_prio_reg *pr = desc->prio_regs + i;
- sh_intc_register(desc, pr->set_reg);
- sh_intc_register(desc, pr->clr_reg);
+ j += sh_intc_register(sysmem, desc,
+ INT_REG_PARAMS(pr, prio, set, j));
+ j += sh_intc_register(sysmem, desc,
+ INT_REG_PARAMS(pr, prio, clr, j));
}
}
+#undef INT_REG_PARAMS
+ /* free unused MemoryRegions */
+ desc->iomem_aliases = g_realloc(desc->iomem_aliases,
+ sizeof(MemoryRegion)*j);
return 0;
}
diff --git a/hw/sh_intc.h b/hw/sh_intc.h
index c117d6f..8916e8c 100644
--- a/hw/sh_intc.h
+++ b/hw/sh_intc.h
@@ -3,6 +3,7 @@
#include "qemu-common.h"
#include "irq.h"
+#include "exec-memory.h"
typedef unsigned char intc_enum;
@@ -46,6 +47,8 @@ struct intc_source {
};
struct intc_desc {
+ MemoryRegion iomem;
+ MemoryRegion *iomem_aliases;
qemu_irq *irqs;
struct intc_source *sources;
int nr_sources;
@@ -53,7 +56,6 @@ struct intc_desc {
int nr_mask_regs;
struct intc_prio_reg *prio_regs;
int nr_prio_regs;
- int iomemtype;
int pending; /* number of interrupt sources that has pending set */
};
@@ -68,7 +70,8 @@ void sh_intc_register_sources(struct intc_desc *desc,
struct intc_group *groups,
int nr_groups);
-int sh_intc_init(struct intc_desc *desc,
+int sh_intc_init(MemoryRegion *sysmem,
+ struct intc_desc *desc,
int nr_sources,
struct intc_mask_reg *mask_regs,
int nr_mask_regs,
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 5a1e15e..f4dda48 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -24,7 +24,10 @@
#include <signal.h>
#include "cpu.h"
+
+#if !defined(CONFIG_USER_ONLY)
#include "hw/sh_intc.h"
+#endif
#if defined(CONFIG_USER_ONLY)
--
1.7.5.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [Qemu-devel] [PATCH 4/5] sh_intc: convert interrupt controller to memory API
2011-11-17 12:24 ` [Qemu-devel] [PATCH 4/5] sh_intc: convert interrupt controller " Benoît Canet
@ 2011-11-17 12:56 ` Peter Maydell
2011-11-17 13:02 ` Avi Kivity
2011-11-17 13:11 ` Benoît Canet
0 siblings, 2 replies; 10+ messages in thread
From: Peter Maydell @ 2011-11-17 12:56 UTC (permalink / raw)
To: Benoît Canet; +Cc: qemu-devel, avi
2011/11/17 Benoît Canet <benoit.canet@gmail.com>:
> Signed-off-by: Benoit Canet <benoit.canet@gmail.com>
> --- a/hw/sh7750.c
> +++ b/hw/sh7750.c
> @@ -756,7 +756,7 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
> "cache-and-tlb", 0x08000000);
> memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem);
>
> - sh_intc_init(&s->intc, NR_SOURCES,
> + sh_intc_init(sysmem, &s->intc, NR_SOURCES,
> _INTC_ARRAY(mask_registers),
> _INTC_ARRAY(prio_registers));
This would be nicer as a sysbus device so we didn't have to hand
it the sysmem, but that can be done later if we care enough I guess.
> + iomem = &desc->iomem;
> + iomem_p4 = desc->iomem_aliases + index;
> + iomem_a7 = iomem_p4 + 1;
> +
> +#define SH_INTC_IOMEM_FORMAT "interrupt-controller-%s-%s-%s"
> + snprintf(name, sizeof(name), SH_INTC_IOMEM_FORMAT, type, action, "p4");
> + memory_region_init_alias(iomem_p4, name, iomem, INTC_A7(address), 4);
> + memory_region_add_subregion(sysmem, P4ADDR(address), iomem_p4);
> +
> + snprintf(name, sizeof(name), SH_INTC_IOMEM_FORMAT, type, action, "a7");
> + memory_region_init_alias(iomem_a7, name, iomem, INTC_A7(address), 4);
> + memory_region_add_subregion(sysmem, A7ADDR(address), iomem_a7);
> +#undef SH_INTC_IOMEM_FORMAT
> +
> + /* used to increment aliases index */
> + return 2;
This is going to give us 6 * 2 * 2 = 24 four-byte memory regions,
incidentally. That should be OK, but one memory region per register
is an interesting arrangement.
> @@ -430,7 +447,11 @@ int sh_intc_init(struct intc_desc *desc,
> desc->nr_mask_regs = nr_mask_regs;
> desc->prio_regs = prio_regs;
> desc->nr_prio_regs = nr_prio_regs;
> + /* Allocate 4 MemoryRegions per register (2 actions * 2 aliases). */
> + desc->iomem_aliases = g_new0(MemoryRegion,
> + (nr_mask_regs + nr_prio_regs) * 4);
This should be exactly the right size...
> + /* free unused MemoryRegions */
> + desc->iomem_aliases = g_realloc(desc->iomem_aliases,
> + sizeof(MemoryRegion)*j);
making this realloc unnecessary; or am I missing something?
-- PMM
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 4/5] sh_intc: convert interrupt controller to memory API
2011-11-17 12:56 ` Peter Maydell
@ 2011-11-17 13:02 ` Avi Kivity
2011-11-17 13:11 ` Benoît Canet
1 sibling, 0 replies; 10+ messages in thread
From: Avi Kivity @ 2011-11-17 13:02 UTC (permalink / raw)
To: Peter Maydell; +Cc: Benoît Canet, qemu-devel
On 11/17/2011 02:56 PM, Peter Maydell wrote:
> 2011/11/17 Benoît Canet <benoit.canet@gmail.com>:
> > Signed-off-by: Benoit Canet <benoit.canet@gmail.com>
> > --- a/hw/sh7750.c
> > +++ b/hw/sh7750.c
> > @@ -756,7 +756,7 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
> > "cache-and-tlb", 0x08000000);
> > memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem);
> >
> > - sh_intc_init(&s->intc, NR_SOURCES,
> > + sh_intc_init(sysmem, &s->intc, NR_SOURCES,
> > _INTC_ARRAY(mask_registers),
> > _INTC_ARRAY(prio_registers));
>
> This would be nicer as a sysbus device so we didn't have to hand
> it the sysmem, but that can be done later if we care enough I guess.
Later, yes.
>
> > + iomem = &desc->iomem;
> > + iomem_p4 = desc->iomem_aliases + index;
> > + iomem_a7 = iomem_p4 + 1;
> > +
> > +#define SH_INTC_IOMEM_FORMAT "interrupt-controller-%s-%s-%s"
> > + snprintf(name, sizeof(name), SH_INTC_IOMEM_FORMAT, type, action, "p4");
> > + memory_region_init_alias(iomem_p4, name, iomem, INTC_A7(address), 4);
> > + memory_region_add_subregion(sysmem, P4ADDR(address), iomem_p4);
> > +
> > + snprintf(name, sizeof(name), SH_INTC_IOMEM_FORMAT, type, action, "a7");
> > + memory_region_init_alias(iomem_a7, name, iomem, INTC_A7(address), 4);
> > + memory_region_add_subregion(sysmem, A7ADDR(address), iomem_a7);
> > +#undef SH_INTC_IOMEM_FORMAT
> > +
> > + /* used to increment aliases index */
> > + return 2;
>
> This is going to give us 6 * 2 * 2 = 24 four-byte memory regions,
> incidentally. That should be OK, but one memory region per register
> is an interesting arrangement.
In fact if we introduce a Register class there's no reason it won't be a
MemoryRegion. So any Register would be a MemoryRegion, we could have
thousands in a system. I don't see anything wrong with it, do you?
>
> > @@ -430,7 +447,11 @@ int sh_intc_init(struct intc_desc *desc,
> > desc->nr_mask_regs = nr_mask_regs;
> > desc->prio_regs = prio_regs;
> > desc->nr_prio_regs = nr_prio_regs;
> > + /* Allocate 4 MemoryRegions per register (2 actions * 2 aliases). */
> > + desc->iomem_aliases = g_new0(MemoryRegion,
> > + (nr_mask_regs + nr_prio_regs) * 4);
>
> This should be exactly the right size...
>
> > + /* free unused MemoryRegions */
> > + desc->iomem_aliases = g_realloc(desc->iomem_aliases,
> > + sizeof(MemoryRegion)*j);
>
> making this realloc unnecessary; or am I missing something?
>
Not all calls to sh_intc_register() return 2.
However, calling realloc() in a MemoryRegion array is not a good idea, since the pointers may leak (memory_region_add_subregion() does this). It's true that a size-reducing realloc doesn't change the pointer, yet it makes me uncomfortable.
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 4/5] sh_intc: convert interrupt controller to memory API
2011-11-17 12:56 ` Peter Maydell
2011-11-17 13:02 ` Avi Kivity
@ 2011-11-17 13:11 ` Benoît Canet
1 sibling, 0 replies; 10+ messages in thread
From: Benoît Canet @ 2011-11-17 13:11 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, avi
[-- Attachment #1: Type: text/plain, Size: 2852 bytes --]
Yes, allocating the exact size would make the realloc unnecessary. But it
involve more code to walk one more time through the mask_reg and prio_reg
array before allocating.
I made it this way to make code shorter.
The freed MemoryRegion are not initialized at all.
However as realloc seems to be a bad idea I need something to compute the
exact size in a minimum of code.
2011/11/17 Peter Maydell <peter.maydell@linaro.org>
> 2011/11/17 Benoît Canet <benoit.canet@gmail.com>:
> > Signed-off-by: Benoit Canet <benoit.canet@gmail.com>
> > --- a/hw/sh7750.c
> > +++ b/hw/sh7750.c
> > @@ -756,7 +756,7 @@ SH7750State *sh7750_init(CPUSH4State * cpu,
> MemoryRegion *sysmem)
> > "cache-and-tlb", 0x08000000);
> > memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem);
> >
> > - sh_intc_init(&s->intc, NR_SOURCES,
> > + sh_intc_init(sysmem, &s->intc, NR_SOURCES,
> > _INTC_ARRAY(mask_registers),
> > _INTC_ARRAY(prio_registers));
>
> This would be nicer as a sysbus device so we didn't have to hand
> it the sysmem, but that can be done later if we care enough I guess.
>
> > + iomem = &desc->iomem;
> > + iomem_p4 = desc->iomem_aliases + index;
> > + iomem_a7 = iomem_p4 + 1;
> > +
> > +#define SH_INTC_IOMEM_FORMAT "interrupt-controller-%s-%s-%s"
> > + snprintf(name, sizeof(name), SH_INTC_IOMEM_FORMAT, type, action,
> "p4");
> > + memory_region_init_alias(iomem_p4, name, iomem, INTC_A7(address),
> 4);
> > + memory_region_add_subregion(sysmem, P4ADDR(address), iomem_p4);
> > +
> > + snprintf(name, sizeof(name), SH_INTC_IOMEM_FORMAT, type, action,
> "a7");
> > + memory_region_init_alias(iomem_a7, name, iomem, INTC_A7(address),
> 4);
> > + memory_region_add_subregion(sysmem, A7ADDR(address), iomem_a7);
> > +#undef SH_INTC_IOMEM_FORMAT
> > +
> > + /* used to increment aliases index */
> > + return 2;
>
> This is going to give us 6 * 2 * 2 = 24 four-byte memory regions,
> incidentally. That should be OK, but one memory region per register
> is an interesting arrangement.
>
> > @@ -430,7 +447,11 @@ int sh_intc_init(struct intc_desc *desc,
> > desc->nr_mask_regs = nr_mask_regs;
> > desc->prio_regs = prio_regs;
> > desc->nr_prio_regs = nr_prio_regs;
> > + /* Allocate 4 MemoryRegions per register (2 actions * 2 aliases). */
> > + desc->iomem_aliases = g_new0(MemoryRegion,
> > + (nr_mask_regs + nr_prio_regs) * 4);
>
> This should be exactly the right size...
>
> > + /* free unused MemoryRegions */
> > + desc->iomem_aliases = g_realloc(desc->iomem_aliases,
> > + sizeof(MemoryRegion)*j);
>
> making this realloc unnecessary; or am I missing something?
>
> -- PMM
>
[-- Attachment #2: Type: text/html, Size: 3922 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Qemu-devel] [PATCH 5/5] sh_serial: convert to memory API
2011-11-17 12:24 [Qemu-devel] [PATCH 0/5] Convert remaining sh4 devices to memory API Benoît Canet
` (3 preceding siblings ...)
2011-11-17 12:24 ` [Qemu-devel] [PATCH 4/5] sh_intc: convert interrupt controller " Benoît Canet
@ 2011-11-17 12:25 ` Benoît Canet
4 siblings, 0 replies; 10+ messages in thread
From: Benoît Canet @ 2011-11-17 12:25 UTC (permalink / raw)
To: qemu-devel; +Cc: Benoît Canet, avi
Signed-off-by: Benoit Canet <benoit.canet@gmail.com>
---
hw/sh.h | 3 ++-
hw/sh7750.c | 28 +++++++++++++++-------------
hw/sh_serial.c | 55 ++++++++++++++++++++++++++++++-------------------------
3 files changed, 47 insertions(+), 39 deletions(-)
diff --git a/hw/sh.h b/hw/sh.h
index c764be6..0e45d61 100644
--- a/hw/sh.h
+++ b/hw/sh.h
@@ -39,7 +39,8 @@ void tmu012_init(struct MemoryRegion *sysmem, target_phys_addr_t base,
/* sh_serial.c */
#define SH_SERIAL_FEAT_SCIF (1 << 0)
-void sh_serial_init (target_phys_addr_t base, int feat,
+void sh_serial_init(MemoryRegion *sysmem,
+ target_phys_addr_t base, int feat,
uint32_t freq, CharDriverState *chr,
qemu_irq eri_source,
qemu_irq rxi_source,
diff --git a/hw/sh7750.c b/hw/sh7750.c
index 930d212..318cdab 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -766,19 +766,21 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
cpu->intc_handle = &s->intc;
- sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0],
- s->intc.irqs[SCI1_ERI],
- s->intc.irqs[SCI1_RXI],
- s->intc.irqs[SCI1_TXI],
- s->intc.irqs[SCI1_TEI],
- NULL);
- sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
- s->periph_freq, serial_hds[1],
- s->intc.irqs[SCIF_ERI],
- s->intc.irqs[SCIF_RXI],
- s->intc.irqs[SCIF_TXI],
- NULL,
- s->intc.irqs[SCIF_BRI]);
+ sh_serial_init(sysmem, 0x1fe00000,
+ 0, s->periph_freq, serial_hds[0],
+ s->intc.irqs[SCI1_ERI],
+ s->intc.irqs[SCI1_RXI],
+ s->intc.irqs[SCI1_TXI],
+ s->intc.irqs[SCI1_TEI],
+ NULL);
+ sh_serial_init(sysmem, 0x1fe80000,
+ SH_SERIAL_FEAT_SCIF,
+ s->periph_freq, serial_hds[1],
+ s->intc.irqs[SCIF_ERI],
+ s->intc.irqs[SCIF_RXI],
+ s->intc.irqs[SCIF_TXI],
+ NULL,
+ s->intc.irqs[SCIF_BRI]);
tmu012_init(sysmem, 0x1fd80000,
TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
diff --git a/hw/sh_serial.c b/hw/sh_serial.c
index a20c59e..43b0eb1 100644
--- a/hw/sh_serial.c
+++ b/hw/sh_serial.c
@@ -27,6 +27,7 @@
#include "hw.h"
#include "sh.h"
#include "qemu-char.h"
+#include "exec-memory.h"
//#define DEBUG_SERIAL
@@ -39,6 +40,9 @@
#define SH_RX_FIFO_LENGTH (16)
typedef struct {
+ MemoryRegion iomem;
+ MemoryRegion iomem_p4;
+ MemoryRegion iomem_a7;
uint8_t smr;
uint8_t brr;
uint8_t scr;
@@ -74,7 +78,8 @@ static void sh_serial_clear_fifo(sh_serial_state * s)
s->rx_tail = 0;
}
-static void sh_serial_write(void *opaque, uint32_t offs, uint32_t val)
+static void sh_serial_write(void *opaque, target_phys_addr_t offs,
+ uint64_t val, unsigned size)
{
sh_serial_state *s = opaque;
unsigned char ch;
@@ -185,7 +190,8 @@ static void sh_serial_write(void *opaque, uint32_t offs, uint32_t val)
abort();
}
-static uint32_t sh_serial_read(void *opaque, uint32_t offs)
+static uint64_t sh_serial_read(void *opaque, target_phys_addr_t offs,
+ unsigned size)
{
sh_serial_state *s = opaque;
uint32_t ret = ~0;
@@ -338,28 +344,22 @@ static void sh_serial_event(void *opaque, int event)
sh_serial_receive_break(s);
}
-static CPUReadMemoryFunc * const sh_serial_readfn[] = {
- &sh_serial_read,
- &sh_serial_read,
- &sh_serial_read,
+static const MemoryRegionOps sh_serial_ops = {
+ .read = sh_serial_read,
+ .write = sh_serial_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const sh_serial_writefn[] = {
- &sh_serial_write,
- &sh_serial_write,
- &sh_serial_write,
-};
-
-void sh_serial_init (target_phys_addr_t base, int feat,
- uint32_t freq, CharDriverState *chr,
- qemu_irq eri_source,
- qemu_irq rxi_source,
- qemu_irq txi_source,
- qemu_irq tei_source,
- qemu_irq bri_source)
+void sh_serial_init(MemoryRegion *sysmem,
+ target_phys_addr_t base, int feat,
+ uint32_t freq, CharDriverState *chr,
+ qemu_irq eri_source,
+ qemu_irq rxi_source,
+ qemu_irq txi_source,
+ qemu_irq tei_source,
+ qemu_irq bri_source)
{
sh_serial_state *s;
- int s_io_memory;
s = g_malloc0(sizeof(sh_serial_state));
@@ -381,11 +381,16 @@ void sh_serial_init (target_phys_addr_t base, int feat,
sh_serial_clear_fifo(s);
- s_io_memory = cpu_register_io_memory(sh_serial_readfn,
- sh_serial_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory);
- cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory);
+ memory_region_init_io(&s->iomem, &sh_serial_ops, s,
+ "serial", 0x100000000ULL);
+
+ memory_region_init_alias(&s->iomem_p4, "serial-p4", &s->iomem,
+ 0, 0x28);
+ memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
+
+ memory_region_init_alias(&s->iomem_a7, "serial-a7", &s->iomem,
+ 0, 0x28);
+ memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
s->chr = chr;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 10+ messages in thread