From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:33012) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RR3Gq-0000ns-Bl for qemu-devel@nongnu.org; Thu, 17 Nov 2011 09:48:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RR3Go-0006TH-I6 for qemu-devel@nongnu.org; Thu, 17 Nov 2011 09:48:56 -0500 Received: from mail-ww0-f53.google.com ([74.125.82.53]:49782) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RR3Go-0006TB-Ag for qemu-devel@nongnu.org; Thu, 17 Nov 2011 09:48:54 -0500 Received: by wwf27 with SMTP id 27so2749936wwf.10 for ; Thu, 17 Nov 2011 06:48:52 -0800 (PST) From: Sasha Levin In-Reply-To: <4EC51BE1.4050002@redhat.com> References: <1321242993-28070-1-git-send-email-zanghongyong@huawei.com> <4EC51BE1.4050002@redhat.com> Content-Type: text/plain; charset="us-ascii" Date: Thu, 17 Nov 2011 16:48:49 +0200 Message-ID: <1321541329.8010.3.camel@lappy> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] ivshmem: use PIO for BAR0(Doorbell) instead of MMIO to reduce notification time List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: louzhengwei@huawei.com, wusongwei@huawei.com, kvm@vger.kernel.org, hanweidong@huawei.com, qemu-devel@nongnu.org, wuchangyi@huawei.com, xiaowei.yang@huawei.com, james.chenjiabo@huawei.com, zanghongyong@huawei.com, cam@cs.ualberta.ca On Thu, 2011-11-17 at 16:36 +0200, Avi Kivity wrote: > On 11/14/2011 05:56 AM, zanghongyong@huawei.com wrote: > > From: Hongyong Zang > > > > Ivshmem(nahanni) is a mechanism for sharing host memory with VMs running on the same host. Currently, guest notifies qemu by reading or writing ivshmem device's PCI MMIO BAR0(Doorbell). > > > > This patch, changes this PCI MMIO BAR0(Doorbell) to PIO. And we find guest accesses PIO BAR 30% faster than MMIO BAR. > > > > CharDriverState **eventfd_chr; > > CharDriverState *server_chr; > > - MemoryRegion ivshmem_mmio; > > + MemoryRegion ivshmem_pio; > > > > - pcibus_t mmio_addr; > > + pcibus_t pio_addr; > > > This is a backwards incompatible change. The way to accomplish this is > to add a new BAR which aliases the old one. The new BAR should not be > visible on guests created with -M pc-1.0 and below. Please also update > the spec so that driver authors can make use of the new feature. Can we add an optional BAR 3 which does exactly what BAR 0 does, but is in PIO space? This will allow us to extend the spec instead of changing it, and in turn drivers could remain compatible with QEMU and other device implementations. -- Sasha.