* [Qemu-devel] [PATCH v2 01/11] mcf5206: convert to memory API
2011-11-22 16:31 [Qemu-devel] [PATCH v2 00/11] more memory API conversion Benoît Canet
@ 2011-11-22 16:31 ` Benoît Canet
2011-11-22 16:31 ` [Qemu-devel] [PATCH v2 02/11] mcf_uart: " Benoît Canet
` (9 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Benoît Canet @ 2011-11-22 16:31 UTC (permalink / raw)
To: qemu-devel; +Cc: Benoît Canet, avi
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
---
hw/an5206.c | 2 +-
hw/mcf.h | 5 ++++-
hw/mcf5206.c | 37 +++++++++++++++++++++----------------
3 files changed, 26 insertions(+), 18 deletions(-)
diff --git a/hw/an5206.c b/hw/an5206.c
index 3fe1f00..319a40e 100644
--- a/hw/an5206.c
+++ b/hw/an5206.c
@@ -53,7 +53,7 @@ static void an5206_init(ram_addr_t ram_size,
memory_region_init_ram(sram, NULL, "an5206.sram", 512);
memory_region_add_subregion(address_space_mem, AN5206_RAMBAR_ADDR, sram);
- mcf5206_init(AN5206_MBAR_ADDR, env);
+ mcf5206_init(address_space_mem, AN5206_MBAR_ADDR, env);
/* Load kernel. */
if (!kernel_filename) {
diff --git a/hw/mcf.h b/hw/mcf.h
index 91f2821..572424d 100644
--- a/hw/mcf.h
+++ b/hw/mcf.h
@@ -2,6 +2,8 @@
#define HW_MCF_H
/* Motorola ColdFire device prototypes. */
+struct MemoryRegion;
+
/* mcf_uart.c */
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
@@ -16,6 +18,7 @@ qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
/* mcf5206.c */
-qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
+qemu_irq *mcf5206_init(struct MemoryRegion *sysmem,
+ uint32_t base, CPUState *env);
#endif
diff --git a/hw/mcf5206.c b/hw/mcf5206.c
index 15d6f22..987687d 100644
--- a/hw/mcf5206.c
+++ b/hw/mcf5206.c
@@ -9,6 +9,7 @@
#include "mcf.h"
#include "qemu-timer.h"
#include "sysemu.h"
+#include "exec-memory.h"
/* General purpose timer module. */
typedef struct {
@@ -144,6 +145,7 @@ static m5206_timer_state *m5206_timer_init(qemu_irq irq)
typedef struct {
CPUState *env;
+ MemoryRegion iomem;
m5206_timer_state *timer[2];
void *uart[2];
uint8_t scr;
@@ -505,29 +507,32 @@ static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
m5206_mbar_write(s, offset, value);
}
-static CPUReadMemoryFunc * const m5206_mbar_readfn[] = {
- m5206_mbar_readb,
- m5206_mbar_readw,
- m5206_mbar_readl
+static const MemoryRegionOps m5206_mbar_ops = {
+ .old_mmio = {
+ .read = {
+ m5206_mbar_readb,
+ m5206_mbar_readw,
+ m5206_mbar_readl,
+ },
+ .write = {
+ m5206_mbar_writeb,
+ m5206_mbar_writew,
+ m5206_mbar_writel,
+ },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const m5206_mbar_writefn[] = {
- m5206_mbar_writeb,
- m5206_mbar_writew,
- m5206_mbar_writel
-};
-
-qemu_irq *mcf5206_init(uint32_t base, CPUState *env)
+qemu_irq *mcf5206_init(MemoryRegion *sysmem, uint32_t base, CPUState *env)
{
m5206_mbar_state *s;
qemu_irq *pic;
- int iomemtype;
s = (m5206_mbar_state *)g_malloc0(sizeof(m5206_mbar_state));
- iomemtype = cpu_register_io_memory(m5206_mbar_readfn,
- m5206_mbar_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x00001000, iomemtype);
+
+ memory_region_init_io(&s->iomem, &m5206_mbar_ops, s,
+ "mbar", 0x00001000);
+ memory_region_add_subregion(sysmem, base, &s->iomem);
pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14);
s->timer[0] = m5206_timer_init(pic[9]);
--
1.7.7.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH v2 02/11] mcf_uart: convert to memory API
2011-11-22 16:31 [Qemu-devel] [PATCH v2 00/11] more memory API conversion Benoît Canet
2011-11-22 16:31 ` [Qemu-devel] [PATCH v2 01/11] mcf5206: convert to memory API Benoît Canet
@ 2011-11-22 16:31 ` Benoît Canet
2011-11-22 16:31 ` [Qemu-devel] [PATCH v2 03/11] mcf_fec: " Benoît Canet
` (8 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Benoît Canet @ 2011-11-22 16:31 UTC (permalink / raw)
To: qemu-devel; +Cc: Benoît Canet, avi
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
---
hw/mcf.h | 11 +++++++----
hw/mcf5206.c | 25 +++++++++++++------------
hw/mcf5208.c | 6 +++---
hw/mcf_uart.c | 34 +++++++++++++++-------------------
4 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/hw/mcf.h b/hw/mcf.h
index 572424d..e2f6727 100644
--- a/hw/mcf.h
+++ b/hw/mcf.h
@@ -5,11 +5,14 @@
struct MemoryRegion;
/* mcf_uart.c */
-uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
-void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
+uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr,
+ unsigned size);
+void mcf_uart_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size);
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
-void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
- CharDriverState *chr);
+void mcf_uart_mm_init(struct MemoryRegion *sysmem,
+ target_phys_addr_t base,
+ qemu_irq irq, CharDriverState *chr);
/* mcf_intc.c */
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
diff --git a/hw/mcf5206.c b/hw/mcf5206.c
index 987687d..7b6d501 100644
--- a/hw/mcf5206.c
+++ b/hw/mcf5206.c
@@ -263,16 +263,17 @@ static void m5206_mbar_reset(m5206_mbar_state *s)
s->par = 0;
}
-static uint32_t m5206_mbar_read(m5206_mbar_state *s, uint32_t offset)
+static uint64_t m5206_mbar_read(m5206_mbar_state *s,
+ uint64_t offset, unsigned size)
{
if (offset >= 0x100 && offset < 0x120) {
return m5206_timer_read(s->timer[0], offset - 0x100);
} else if (offset >= 0x120 && offset < 0x140) {
return m5206_timer_read(s->timer[1], offset - 0x120);
} else if (offset >= 0x140 && offset < 0x160) {
- return mcf_uart_read(s->uart[0], offset - 0x140);
+ return mcf_uart_read(s->uart[0], offset - 0x140, size);
} else if (offset >= 0x180 && offset < 0x1a0) {
- return mcf_uart_read(s->uart[1], offset - 0x180);
+ return mcf_uart_read(s->uart[1], offset - 0x180, size);
}
switch (offset) {
case 0x03: return s->scr;
@@ -301,7 +302,7 @@ static uint32_t m5206_mbar_read(m5206_mbar_state *s, uint32_t offset)
}
static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
if (offset >= 0x100 && offset < 0x120) {
m5206_timer_write(s->timer[0], offset - 0x100, value);
@@ -310,10 +311,10 @@ static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset,
m5206_timer_write(s->timer[1], offset - 0x120, value);
return;
} else if (offset >= 0x140 && offset < 0x160) {
- mcf_uart_write(s->uart[0], offset - 0x140, value);
+ mcf_uart_write(s->uart[0], offset - 0x140, value, size);
return;
} else if (offset >= 0x180 && offset < 0x1a0) {
- mcf_uart_write(s->uart[1], offset - 0x180, value);
+ mcf_uart_write(s->uart[1], offset - 0x180, value, size);
return;
}
switch (offset) {
@@ -387,7 +388,7 @@ static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset)
}
return val & 0xff;
}
- return m5206_mbar_read(s, offset);
+ return m5206_mbar_read(s, offset, 1);
}
static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
@@ -411,7 +412,7 @@ static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
val |= m5206_mbar_readb(opaque, offset + 1);
return val;
}
- return m5206_mbar_read(s, offset);
+ return m5206_mbar_read(s, offset, 2);
}
static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
@@ -429,7 +430,7 @@ static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
val |= m5206_mbar_readw(opaque, offset + 2);
return val;
}
- return m5206_mbar_read(s, offset);
+ return m5206_mbar_read(s, offset, 4);
}
static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
@@ -458,7 +459,7 @@ static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset,
m5206_mbar_writew(opaque, offset & ~1, tmp);
return;
}
- m5206_mbar_write(s, offset, value);
+ m5206_mbar_write(s, offset, value, 1);
}
static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
@@ -486,7 +487,7 @@ static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
m5206_mbar_writeb(opaque, offset + 1, value & 0xff);
return;
}
- m5206_mbar_write(s, offset, value);
+ m5206_mbar_write(s, offset, value, 2);
}
static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
@@ -504,7 +505,7 @@ static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
m5206_mbar_writew(opaque, offset + 2, value & 0xffff);
return;
}
- m5206_mbar_write(s, offset, value);
+ m5206_mbar_write(s, offset, value, 4);
}
static const MemoryRegionOps m5206_mbar_ops = {
diff --git a/hw/mcf5208.c b/hw/mcf5208.c
index 1c2c0c4..0119430 100644
--- a/hw/mcf5208.c
+++ b/hw/mcf5208.c
@@ -223,9 +223,9 @@ static void mcf5208evb_init(ram_addr_t ram_size,
/* Internal peripherals. */
pic = mcf_intc_init(0xfc048000, env);
- mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]);
- mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]);
- mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]);
+ mcf_uart_mm_init(address_space_mem, 0xfc060000, pic[26], serial_hds[0]);
+ mcf_uart_mm_init(address_space_mem, 0xfc064000, pic[27], serial_hds[1]);
+ mcf_uart_mm_init(address_space_mem, 0xfc068000, pic[28], serial_hds[2]);
mcf5208_sys_init(address_space_mem, pic);
diff --git a/hw/mcf_uart.c b/hw/mcf_uart.c
index e6b2ab0..ec6a87f 100644
--- a/hw/mcf_uart.c
+++ b/hw/mcf_uart.c
@@ -8,8 +8,10 @@
#include "hw.h"
#include "mcf.h"
#include "qemu-char.h"
+#include "exec-memory.h"
typedef struct {
+ MemoryRegion iomem;
uint8_t mr[2];
uint8_t sr;
uint8_t isr;
@@ -64,7 +66,8 @@ static void mcf_uart_update(mcf_uart_state *s)
qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
}
-uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr)
+uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
switch (addr & 0x3f) {
@@ -182,7 +185,8 @@ static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
}
}
-void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val)
+void mcf_uart_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
switch (addr & 0x3f) {
@@ -283,28 +287,20 @@ void *mcf_uart_init(qemu_irq irq, CharDriverState *chr)
return s;
}
-
-static CPUReadMemoryFunc * const mcf_uart_readfn[] = {
- mcf_uart_read,
- mcf_uart_read,
- mcf_uart_read
-};
-
-static CPUWriteMemoryFunc * const mcf_uart_writefn[] = {
- mcf_uart_write,
- mcf_uart_write,
- mcf_uart_write
+static const MemoryRegionOps mcf_uart_ops = {
+ .read = mcf_uart_read,
+ .write = mcf_uart_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
+void mcf_uart_mm_init(MemoryRegion *sysmem,
+ target_phys_addr_t base,
+ qemu_irq irq,
CharDriverState *chr)
{
mcf_uart_state *s;
- int iomemtype;
s = mcf_uart_init(irq, chr);
- iomemtype = cpu_register_io_memory(mcf_uart_readfn,
- mcf_uart_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x40, iomemtype);
+ memory_region_init_io(&s->iomem, &mcf_uart_ops, s, "uart", 0x40);
+ memory_region_add_subregion(sysmem, base, &s->iomem);
}
--
1.7.7.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH v2 03/11] mcf_fec: convert to memory API
2011-11-22 16:31 [Qemu-devel] [PATCH v2 00/11] more memory API conversion Benoît Canet
2011-11-22 16:31 ` [Qemu-devel] [PATCH v2 01/11] mcf5206: convert to memory API Benoît Canet
2011-11-22 16:31 ` [Qemu-devel] [PATCH v2 02/11] mcf_uart: " Benoît Canet
@ 2011-11-22 16:31 ` Benoît Canet
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 04/11] mcf_intc: " Benoît Canet
` (7 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Benoît Canet @ 2011-11-22 16:31 UTC (permalink / raw)
To: qemu-devel; +Cc: Benoît Canet, avi
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
---
hw/mcf.h | 3 ++-
hw/mcf5208.c | 3 ++-
hw/mcf_fec.c | 38 +++++++++++++++++++-------------------
3 files changed, 23 insertions(+), 21 deletions(-)
diff --git a/hw/mcf.h b/hw/mcf.h
index e2f6727..2f88ff0 100644
--- a/hw/mcf.h
+++ b/hw/mcf.h
@@ -18,7 +18,8 @@ void mcf_uart_mm_init(struct MemoryRegion *sysmem,
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
/* mcf_fec.c */
-void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
+void mcf_fec_init(struct MemoryRegion *sysmem, NICInfo *nd,
+ target_phys_addr_t base, qemu_irq *irq);
/* mcf5206.c */
qemu_irq *mcf5206_init(struct MemoryRegion *sysmem,
diff --git a/hw/mcf5208.c b/hw/mcf5208.c
index 0119430..e03d80b 100644
--- a/hw/mcf5208.c
+++ b/hw/mcf5208.c
@@ -234,7 +234,8 @@ static void mcf5208evb_init(ram_addr_t ram_size,
exit(1);
}
if (nd_table[0].vlan)
- mcf_fec_init(&nd_table[0], 0xfc030000, pic + 36);
+ mcf_fec_init(address_space_mem, &nd_table[0],
+ 0xfc030000, pic + 36);
/* 0xfc000000 SCM. */
/* 0xfc004000 XBS. */
diff --git a/hw/mcf_fec.c b/hw/mcf_fec.c
index 42a5d77..ae37bef 100644
--- a/hw/mcf_fec.c
+++ b/hw/mcf_fec.c
@@ -10,6 +10,7 @@
#include "mcf.h"
/* For crc32 */
#include <zlib.h>
+#include "exec-memory.h"
//#define DEBUG_FEC 1
@@ -23,8 +24,9 @@ do { printf("mcf_fec: " fmt , ## __VA_ARGS__); } while (0)
#define FEC_MAX_FRAME_SIZE 2032
typedef struct {
+ MemoryRegion *sysmem;
+ MemoryRegion iomem;
qemu_irq *irq;
- int mmio_index;
NICState *nic;
NICConf conf;
uint32_t irq_state;
@@ -214,7 +216,8 @@ static void mcf_fec_reset(mcf_fec_state *s)
s->rfsr = 0x500;
}
-static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr)
+static uint64_t mcf_fec_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
switch (addr & 0x3ff) {
@@ -251,7 +254,8 @@ static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr)
}
}
-static void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void mcf_fec_write(void *opaque, target_phys_addr_t addr,
+ uint64_t value, unsigned size)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
switch (addr & 0x3ff) {
@@ -429,23 +433,18 @@ static ssize_t mcf_fec_receive(VLANClientState *nc, const uint8_t *buf, size_t s
return size;
}
-static CPUReadMemoryFunc * const mcf_fec_readfn[] = {
- mcf_fec_read,
- mcf_fec_read,
- mcf_fec_read
-};
-
-static CPUWriteMemoryFunc * const mcf_fec_writefn[] = {
- mcf_fec_write,
- mcf_fec_write,
- mcf_fec_write
+static const MemoryRegionOps mcf_fec_ops = {
+ .read = mcf_fec_read,
+ .write = mcf_fec_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void mcf_fec_cleanup(VLANClientState *nc)
{
mcf_fec_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
- cpu_unregister_io_memory(s->mmio_index);
+ memory_region_del_subregion(s->sysmem, &s->iomem);
+ memory_region_destroy(&s->iomem);
g_free(s);
}
@@ -458,18 +457,19 @@ static NetClientInfo net_mcf_fec_info = {
.cleanup = mcf_fec_cleanup,
};
-void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq)
+void mcf_fec_init(MemoryRegion *sysmem, NICInfo *nd,
+ target_phys_addr_t base, qemu_irq *irq)
{
mcf_fec_state *s;
qemu_check_nic_model(nd, "mcf_fec");
s = (mcf_fec_state *)g_malloc0(sizeof(mcf_fec_state));
+ s->sysmem = sysmem;
s->irq = irq;
- s->mmio_index = cpu_register_io_memory(mcf_fec_readfn,
- mcf_fec_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x400, s->mmio_index);
+
+ memory_region_init_io(&s->iomem, &mcf_fec_ops, s, "fec", 0x400);
+ memory_region_add_subregion(sysmem, base, &s->iomem);
s->conf.macaddr = nd->macaddr;
s->conf.vlan = nd->vlan;
--
1.7.7.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH v2 04/11] mcf_intc: convert to memory API
2011-11-22 16:31 [Qemu-devel] [PATCH v2 00/11] more memory API conversion Benoît Canet
` (2 preceding siblings ...)
2011-11-22 16:31 ` [Qemu-devel] [PATCH v2 03/11] mcf_fec: " Benoît Canet
@ 2011-11-22 16:32 ` Benoît Canet
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 05/11] lm32_uart: " Benoît Canet
` (6 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Benoît Canet @ 2011-11-22 16:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Benoît Canet, avi
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
---
hw/mcf.h | 4 +++-
hw/mcf5208.c | 2 +-
hw/mcf_intc.c | 33 +++++++++++++++------------------
3 files changed, 19 insertions(+), 20 deletions(-)
diff --git a/hw/mcf.h b/hw/mcf.h
index 2f88ff0..baa790b 100644
--- a/hw/mcf.h
+++ b/hw/mcf.h
@@ -15,7 +15,9 @@ void mcf_uart_mm_init(struct MemoryRegion *sysmem,
qemu_irq irq, CharDriverState *chr);
/* mcf_intc.c */
-qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
+qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
+ target_phys_addr_t base,
+ CPUState *env);
/* mcf_fec.c */
void mcf_fec_init(struct MemoryRegion *sysmem, NICInfo *nd,
diff --git a/hw/mcf5208.c b/hw/mcf5208.c
index e03d80b..ec608a1 100644
--- a/hw/mcf5208.c
+++ b/hw/mcf5208.c
@@ -221,7 +221,7 @@ static void mcf5208evb_init(ram_addr_t ram_size,
memory_region_add_subregion(address_space_mem, 0x80000000, sram);
/* Internal peripherals. */
- pic = mcf_intc_init(0xfc048000, env);
+ pic = mcf_intc_init(address_space_mem, 0xfc048000, env);
mcf_uart_mm_init(address_space_mem, 0xfc060000, pic[26], serial_hds[0]);
mcf_uart_mm_init(address_space_mem, 0xfc064000, pic[27], serial_hds[1]);
diff --git a/hw/mcf_intc.c b/hw/mcf_intc.c
index 99092e7..0b498dd 100644
--- a/hw/mcf_intc.c
+++ b/hw/mcf_intc.c
@@ -7,8 +7,10 @@
*/
#include "hw.h"
#include "mcf.h"
+#include "exec-memory.h"
typedef struct {
+ MemoryRegion iomem;
uint64_t ipr;
uint64_t imr;
uint64_t ifr;
@@ -41,7 +43,8 @@ static void mcf_intc_update(mcf_intc_state *s)
m68k_set_irq_level(s->env, best_level, s->active_vector);
}
-static uint32_t mcf_intc_read(void *opaque, target_phys_addr_t addr)
+static uint64_t mcf_intc_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
int offset;
mcf_intc_state *s = (mcf_intc_state *)opaque;
@@ -73,7 +76,8 @@ static uint32_t mcf_intc_read(void *opaque, target_phys_addr_t addr)
}
}
-static void mcf_intc_write(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void mcf_intc_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
int offset;
mcf_intc_state *s = (mcf_intc_state *)opaque;
@@ -127,31 +131,24 @@ static void mcf_intc_reset(mcf_intc_state *s)
s->active_vector = 24;
}
-static CPUReadMemoryFunc * const mcf_intc_readfn[] = {
- mcf_intc_read,
- mcf_intc_read,
- mcf_intc_read
+static const MemoryRegionOps mcf_intc_ops = {
+ .read = mcf_intc_read,
+ .write = mcf_intc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const mcf_intc_writefn[] = {
- mcf_intc_write,
- mcf_intc_write,
- mcf_intc_write
-};
-
-qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env)
+qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
+ target_phys_addr_t base,
+ CPUState *env)
{
mcf_intc_state *s;
- int iomemtype;
s = g_malloc0(sizeof(mcf_intc_state));
s->env = env;
mcf_intc_reset(s);
- iomemtype = cpu_register_io_memory(mcf_intc_readfn,
- mcf_intc_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x100, iomemtype);
+ memory_region_init_io(&s->iomem, &mcf_intc_ops, s, "mcf", 0x100);
+ memory_region_add_subregion(sysmem, base, &s->iomem);
return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);
}
--
1.7.7.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH v2 05/11] lm32_uart: convert to memory API
2011-11-22 16:31 [Qemu-devel] [PATCH v2 00/11] more memory API conversion Benoît Canet
` (3 preceding siblings ...)
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 04/11] mcf_intc: " Benoît Canet
@ 2011-11-22 16:32 ` Benoît Canet
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 06/11] lm32_sys: " Benoît Canet
` (5 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Benoît Canet @ 2011-11-22 16:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Benoît Canet, avi
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
---
hw/lm32_uart.c | 31 +++++++++++++++----------------
1 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/hw/lm32_uart.c b/hw/lm32_uart.c
index 3678545..46a5ae0 100644
--- a/hw/lm32_uart.c
+++ b/hw/lm32_uart.c
@@ -91,6 +91,7 @@ enum {
struct LM32UartState {
SysBusDevice busdev;
+ MemoryRegion iomem;
CharDriverState *chr;
qemu_irq irq;
@@ -124,7 +125,8 @@ static void uart_update_irq(LM32UartState *s)
qemu_set_irq(s->irq, irq);
}
-static uint32_t uart_read(void *opaque, target_phys_addr_t addr)
+static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
LM32UartState *s = opaque;
uint32_t r = 0;
@@ -158,7 +160,8 @@ static uint32_t uart_read(void *opaque, target_phys_addr_t addr)
return r;
}
-static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void uart_write(void *opaque, target_phys_addr_t addr,
+ uint64_t value, unsigned size)
{
LM32UartState *s = opaque;
unsigned char ch = value;
@@ -192,16 +195,14 @@ static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value)
uart_update_irq(s);
}
-static CPUReadMemoryFunc * const uart_read_fn[] = {
- NULL,
- NULL,
- &uart_read,
-};
-
-static CPUWriteMemoryFunc * const uart_write_fn[] = {
- NULL,
- NULL,
- &uart_write,
+static const MemoryRegionOps uart_ops = {
+ .read = uart_read,
+ .write = uart_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static void uart_rx(void *opaque, const uint8_t *buf, int size)
@@ -245,13 +246,11 @@ static void uart_reset(DeviceState *d)
static int lm32_uart_init(SysBusDevice *dev)
{
LM32UartState *s = FROM_SYSBUS(typeof(*s), dev);
- int uart_regs;
sysbus_init_irq(dev, &s->irq);
- uart_regs = cpu_register_io_memory(uart_read_fn, uart_write_fn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, R_MAX * 4, uart_regs);
+ memory_region_init_io(&s->iomem, &uart_ops, s, "uart", R_MAX * 4);
+ sysbus_init_mmio_region(dev, &s->iomem);
s->chr = qdev_init_chardev(&dev->qdev);
if (s->chr) {
--
1.7.7.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH v2 06/11] lm32_sys: convert to memory API
2011-11-22 16:31 [Qemu-devel] [PATCH v2 00/11] more memory API conversion Benoît Canet
` (4 preceding siblings ...)
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 05/11] lm32_uart: " Benoît Canet
@ 2011-11-22 16:32 ` Benoît Canet
2011-11-22 17:36 ` Avi Kivity
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 07/11] bonito: convert north bridge register mapping " Benoît Canet
` (4 subsequent siblings)
10 siblings, 1 reply; 13+ messages in thread
From: Benoît Canet @ 2011-11-22 16:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Benoît Canet, avi
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
---
hw/lm32_sys.c | 23 +++++++++--------------
1 files changed, 9 insertions(+), 14 deletions(-)
diff --git a/hw/lm32_sys.c b/hw/lm32_sys.c
index e5ff962..6aa8b2e 100644
--- a/hw/lm32_sys.c
+++ b/hw/lm32_sys.c
@@ -47,6 +47,7 @@ enum {
struct LM32SysState {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t base;
uint32_t regs[R_MAX];
uint8_t testname[MAX_TESTNAME_LEN];
@@ -89,16 +90,12 @@ static void sys_write(void *opaque, target_phys_addr_t addr, uint32_t value)
}
}
-static CPUReadMemoryFunc * const sys_read_fn[] = {
- NULL,
- NULL,
- NULL,
-};
-
-static CPUWriteMemoryFunc * const sys_write_fn[] = {
- NULL,
- NULL,
- &sys_write,
+static const MemoryRegionOps sys_ops = {
+ .old_mmio = {
+ .read = { NULL, NULL, NULL, },
+ .write = { NULL, NULL, sys_write, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void sys_reset(DeviceState *d)
@@ -115,11 +112,9 @@ static void sys_reset(DeviceState *d)
static int lm32_sys_init(SysBusDevice *dev)
{
LM32SysState *s = FROM_SYSBUS(typeof(*s), dev);
- int sys_regs;
- sys_regs = cpu_register_io_memory(sys_read_fn, sys_write_fn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, R_MAX * 4, sys_regs);
+ memory_region_init_io(&s->iomem, &sys_ops , s, "sys", R_MAX * 4);
+ sysbus_init_mmio_region(dev, &s->iomem);
/* Note: This device is not created in the board initialization,
* instead it has to be added with the -device parameter. Therefore,
--
1.7.7.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PATCH v2 06/11] lm32_sys: convert to memory API
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 06/11] lm32_sys: " Benoît Canet
@ 2011-11-22 17:36 ` Avi Kivity
0 siblings, 0 replies; 13+ messages in thread
From: Avi Kivity @ 2011-11-22 17:36 UTC (permalink / raw)
To: Benoît Canet; +Cc: qemu-devel
On 11/22/2011 06:32 PM, Benoît Canet wrote:
>
> -static CPUReadMemoryFunc * const sys_read_fn[] = {
> - NULL,
> - NULL,
> - NULL,
> -};
> -
> -static CPUWriteMemoryFunc * const sys_write_fn[] = {
> - NULL,
> - NULL,
> - &sys_write,
> +static const MemoryRegionOps sys_ops = {
> + .old_mmio = {
> + .read = { NULL, NULL, NULL, },
> + .write = { NULL, NULL, sys_write, },
> + },
> + .endianness = DEVICE_NATIVE_ENDIAN,
> };
Please use .valid.accepts for cases like this.
--
error compiling committee.c: too many arguments to function
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH v2 07/11] bonito: convert north bridge register mapping to memory API
2011-11-22 16:31 [Qemu-devel] [PATCH v2 00/11] more memory API conversion Benoît Canet
` (5 preceding siblings ...)
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 06/11] lm32_sys: " Benoît Canet
@ 2011-11-22 16:32 ` Benoît Canet
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 08/11] bonito: convert north bridge pci config " Benoît Canet
` (3 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Benoît Canet @ 2011-11-22 16:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Benoît Canet, avi
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
---
hw/bonito.c | 39 ++++++++++++++++++---------------------
1 files changed, 18 insertions(+), 21 deletions(-)
diff --git a/hw/bonito.c b/hw/bonito.c
index fdb8198..9260848 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -201,9 +201,7 @@ typedef struct PCIBonitoState
} boncop;
/* Bonito registers */
- target_phys_addr_t bonito_reg_start;
- target_phys_addr_t bonito_reg_length;
- int bonito_reg_handle;
+ MemoryRegion iomem;
target_phys_addr_t bonito_pciconf_start;
target_phys_addr_t bonito_pciconf_length;
@@ -233,7 +231,8 @@ typedef struct PCIBonitoState
PCIBonitoState * bonito_state;
-static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void bonito_writel(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
uint32_t saddr;
@@ -295,7 +294,8 @@ static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
}
}
-static uint32_t bonito_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t bonito_readl(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
PCIBonitoState *s = opaque;
uint32_t saddr;
@@ -311,16 +311,14 @@ static uint32_t bonito_readl(void *opaque, target_phys_addr_t addr)
}
}
-static CPUWriteMemoryFunc * const bonito_write[] = {
- NULL,
- NULL,
- bonito_writel,
-};
-
-static CPUReadMemoryFunc * const bonito_read[] = {
- NULL,
- NULL,
- bonito_readl,
+static const MemoryRegionOps bonito_ops = {
+ .read = bonito_readl,
+ .write = bonito_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
@@ -690,17 +688,16 @@ static int bonito_pcihost_initfn(SysBusDevice *dev)
static int bonito_initfn(PCIDevice *dev)
{
PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev);
+ SysBusDevice *sysbus = sysbus_from_qdev(&dev->qdev);
/* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */
pci_config_set_prog_interface(dev->config, 0x00);
/* set the north bridge register mapping */
- s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s,
- DEVICE_NATIVE_ENDIAN);
- s->bonito_reg_start = BONITO_INTERNAL_REG_BASE;
- s->bonito_reg_length = BONITO_INTERNAL_REG_SIZE;
- cpu_register_physical_memory(s->bonito_reg_start, s->bonito_reg_length,
- s->bonito_reg_handle);
+ memory_region_init_io(&s->iomem, &bonito_ops, s,
+ "north-bridge-register", BONITO_INTERNAL_REG_SIZE);
+ sysbus_init_mmio_region(sysbus, &s->iomem);
+ sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE);
/* set the north bridge pci configure mapping */
s->bonito_pciconf_handle = cpu_register_io_memory(bonito_pciconf_read,
--
1.7.7.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH v2 08/11] bonito: convert north bridge pci config to memory API
2011-11-22 16:31 [Qemu-devel] [PATCH v2 00/11] more memory API conversion Benoît Canet
` (6 preceding siblings ...)
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 07/11] bonito: convert north bridge register mapping " Benoît Canet
@ 2011-11-22 16:32 ` Benoît Canet
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 09/11] bonito: convert south " Benoît Canet
` (2 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Benoît Canet @ 2011-11-22 16:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Benoît Canet, avi
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
---
hw/bonito.c | 38 ++++++++++++++++----------------------
1 files changed, 16 insertions(+), 22 deletions(-)
diff --git a/hw/bonito.c b/hw/bonito.c
index 9260848..8fa709a 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -202,10 +202,7 @@ typedef struct PCIBonitoState
/* Bonito registers */
MemoryRegion iomem;
-
- target_phys_addr_t bonito_pciconf_start;
- target_phys_addr_t bonito_pciconf_length;
- int bonito_pciconf_handle;
+ MemoryRegion iomem_pciconf;
target_phys_addr_t bonito_spciconf_start;
target_phys_addr_t bonito_spciconf_length;
@@ -322,7 +319,7 @@ static const MemoryRegionOps bonito_ops = {
};
static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
@@ -330,7 +327,8 @@ static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
s->dev.config_write(&s->dev, addr, val, 4);
}
-static uint32_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
PCIBonitoState *s = opaque;
@@ -340,16 +338,15 @@ static uint32_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr)
}
/* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
-static CPUWriteMemoryFunc * const bonito_pciconf_write[] = {
- NULL,
- NULL,
- bonito_pciconf_writel,
-};
-static CPUReadMemoryFunc * const bonito_pciconf_read[] = {
- NULL,
- NULL,
- bonito_pciconf_readl,
+static const MemoryRegionOps bonito_pciconf_ops = {
+ .read = bonito_pciconf_readl,
+ .write = bonito_pciconf_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static uint32_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr)
@@ -700,13 +697,10 @@ static int bonito_initfn(PCIDevice *dev)
sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE);
/* set the north bridge pci configure mapping */
- s->bonito_pciconf_handle = cpu_register_io_memory(bonito_pciconf_read,
- bonito_pciconf_write, s,
- DEVICE_NATIVE_ENDIAN);
- s->bonito_pciconf_start = BONITO_PCICONFIG_BASE;
- s->bonito_pciconf_length = BONITO_PCICONFIG_SIZE;
- cpu_register_physical_memory(s->bonito_pciconf_start, s->bonito_pciconf_length,
- s->bonito_pciconf_handle);
+ memory_region_init_io(&s->iomem_pciconf, &bonito_pciconf_ops, s,
+ "north-bridge-pci-config", BONITO_PCICONFIG_SIZE);
+ sysbus_init_mmio_region(sysbus, &s->iomem_pciconf);
+ sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE);
/* set the south bridge pci configure mapping */
s->bonito_spciconf_handle = cpu_register_io_memory(bonito_spciconf_read,
--
1.7.7.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH v2 09/11] bonito: convert south bridge pci config to memory API
2011-11-22 16:31 [Qemu-devel] [PATCH v2 00/11] more memory API conversion Benoît Canet
` (7 preceding siblings ...)
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 08/11] bonito: convert north bridge pci config " Benoît Canet
@ 2011-11-22 16:32 ` Benoît Canet
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 10/11] bonito: convert ldma " Benoît Canet
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 11/11] bonito: convert cop " Benoît Canet
10 siblings, 0 replies; 13+ messages in thread
From: Benoît Canet @ 2011-11-22 16:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Benoît Canet, avi
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
---
hw/bonito.c | 40 +++++++++++++++++++---------------------
1 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/hw/bonito.c b/hw/bonito.c
index 8fa709a..b4c3387 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -203,10 +203,7 @@ typedef struct PCIBonitoState
/* Bonito registers */
MemoryRegion iomem;
MemoryRegion iomem_pciconf;
-
- target_phys_addr_t bonito_spciconf_start;
- target_phys_addr_t bonito_spciconf_length;
- int bonito_spciconf_handle;
+ MemoryRegion iomem_spciconf;
target_phys_addr_t bonito_pciio_start;
target_phys_addr_t bonito_pciio_length;
@@ -597,16 +594,20 @@ static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr)
}
/* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
-static CPUWriteMemoryFunc * const bonito_spciconf_write[] = {
- bonito_spciconf_writeb,
- bonito_spciconf_writew,
- bonito_spciconf_writel,
-};
-
-static CPUReadMemoryFunc * const bonito_spciconf_read[] = {
- bonito_spciconf_readb,
- bonito_spciconf_readw,
- bonito_spciconf_readl,
+static const MemoryRegionOps bonito_spciconf_ops = {
+ .old_mmio = {
+ .read = {
+ bonito_spciconf_readb,
+ bonito_spciconf_readw,
+ bonito_spciconf_readl,
+ },
+ .write = {
+ bonito_spciconf_writeb,
+ bonito_spciconf_writew,
+ bonito_spciconf_writel,
+ },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
#define BONITO_IRQ_BASE 32
@@ -703,13 +704,10 @@ static int bonito_initfn(PCIDevice *dev)
sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE);
/* set the south bridge pci configure mapping */
- s->bonito_spciconf_handle = cpu_register_io_memory(bonito_spciconf_read,
- bonito_spciconf_write, s,
- DEVICE_NATIVE_ENDIAN);
- s->bonito_spciconf_start = BONITO_SPCICONFIG_BASE;
- s->bonito_spciconf_length = BONITO_SPCICONFIG_SIZE;
- cpu_register_physical_memory(s->bonito_spciconf_start, s->bonito_spciconf_length,
- s->bonito_spciconf_handle);
+ memory_region_init_io(&s->iomem_spciconf, &bonito_spciconf_ops, s,
+ "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
+ sysbus_init_mmio_region(sysbus, &s->iomem_spciconf);
+ sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE);
s->bonito_ldma_handle = cpu_register_io_memory(bonito_ldma_read,
bonito_ldma_write, s,
--
1.7.7.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH v2 10/11] bonito: convert ldma to memory API
2011-11-22 16:31 [Qemu-devel] [PATCH v2 00/11] more memory API conversion Benoît Canet
` (8 preceding siblings ...)
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 09/11] bonito: convert south " Benoît Canet
@ 2011-11-22 16:32 ` Benoît Canet
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 11/11] bonito: convert cop " Benoît Canet
10 siblings, 0 replies; 13+ messages in thread
From: Benoît Canet @ 2011-11-22 16:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Benoît Canet, avi
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
---
hw/bonito.c | 39 ++++++++++++++++-----------------------
1 files changed, 16 insertions(+), 23 deletions(-)
diff --git a/hw/bonito.c b/hw/bonito.c
index b4c3387..8972f55 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -204,6 +204,7 @@ typedef struct PCIBonitoState
MemoryRegion iomem;
MemoryRegion iomem_pciconf;
MemoryRegion iomem_spciconf;
+ MemoryRegion iomem_ldma;
target_phys_addr_t bonito_pciio_start;
target_phys_addr_t bonito_pciio_length;
@@ -213,10 +214,6 @@ typedef struct PCIBonitoState
target_phys_addr_t bonito_localio_length;
int bonito_localio_handle;
- target_phys_addr_t bonito_ldma_start;
- target_phys_addr_t bonito_ldma_length;
- int bonito_ldma_handle;
-
target_phys_addr_t bonito_cop_start;
target_phys_addr_t bonito_cop_length;
int bonito_cop_handle;
@@ -346,7 +343,8 @@ static const MemoryRegionOps bonito_pciconf_ops = {
},
};
-static uint32_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
uint32_t val;
PCIBonitoState *s = opaque;
@@ -357,23 +355,21 @@ static uint32_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr)
}
static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff;
}
-static CPUWriteMemoryFunc * const bonito_ldma_write[] = {
- NULL,
- NULL,
- bonito_ldma_writel,
-};
-
-static CPUReadMemoryFunc * const bonito_ldma_read[] = {
- NULL,
- NULL,
- bonito_ldma_readl,
+static const MemoryRegionOps bonito_ldma_ops = {
+ .read = bonito_ldma_readl,
+ .write = bonito_ldma_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static uint32_t bonito_cop_readl(void *opaque, target_phys_addr_t addr)
@@ -709,13 +705,10 @@ static int bonito_initfn(PCIDevice *dev)
sysbus_init_mmio_region(sysbus, &s->iomem_spciconf);
sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE);
- s->bonito_ldma_handle = cpu_register_io_memory(bonito_ldma_read,
- bonito_ldma_write, s,
- DEVICE_NATIVE_ENDIAN);
- s->bonito_ldma_start = 0xbfe00200;
- s->bonito_ldma_length = 0x100;
- cpu_register_physical_memory(s->bonito_ldma_start, s->bonito_ldma_length,
- s->bonito_ldma_handle);
+ memory_region_init_io(&s->iomem_ldma, &bonito_ldma_ops, s,
+ "ldma", 0x100);
+ sysbus_init_mmio_region(sysbus, &s->iomem_ldma);
+ sysbus_mmio_map(sysbus, 3, 0xbfe00200);
s->bonito_cop_handle = cpu_register_io_memory(bonito_cop_read,
bonito_cop_write, s,
--
1.7.7.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH v2 11/11] bonito: convert cop to memory API
2011-11-22 16:31 [Qemu-devel] [PATCH v2 00/11] more memory API conversion Benoît Canet
` (9 preceding siblings ...)
2011-11-22 16:32 ` [Qemu-devel] [PATCH v2 10/11] bonito: convert ldma " Benoît Canet
@ 2011-11-22 16:32 ` Benoît Canet
10 siblings, 0 replies; 13+ messages in thread
From: Benoît Canet @ 2011-11-22 16:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Benoît Canet, avi
Signed-off-by: Benoît Canet <benoit.canet@gmail.com>
---
hw/bonito.c | 40 +++++++++++++++++-----------------------
1 files changed, 17 insertions(+), 23 deletions(-)
diff --git a/hw/bonito.c b/hw/bonito.c
index 8972f55..a92675c 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -205,6 +205,7 @@ typedef struct PCIBonitoState
MemoryRegion iomem_pciconf;
MemoryRegion iomem_spciconf;
MemoryRegion iomem_ldma;
+ MemoryRegion iomem_cop;
target_phys_addr_t bonito_pciio_start;
target_phys_addr_t bonito_pciio_length;
@@ -214,10 +215,6 @@ typedef struct PCIBonitoState
target_phys_addr_t bonito_localio_length;
int bonito_localio_handle;
- target_phys_addr_t bonito_cop_start;
- target_phys_addr_t bonito_cop_length;
- int bonito_cop_handle;
-
} PCIBonitoState;
PCIBonitoState * bonito_state;
@@ -372,7 +369,8 @@ static const MemoryRegionOps bonito_ldma_ops = {
},
};
-static uint32_t bonito_cop_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t bonito_cop_readl(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
uint32_t val;
PCIBonitoState *s = opaque;
@@ -383,23 +381,21 @@ static uint32_t bonito_cop_readl(void *opaque, target_phys_addr_t addr)
}
static void bonito_cop_writel(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff;
}
-static CPUWriteMemoryFunc * const bonito_cop_write[] = {
- NULL,
- NULL,
- bonito_cop_writel,
-};
-
-static CPUReadMemoryFunc * const bonito_cop_read[] = {
- NULL,
- NULL,
- bonito_cop_readl,
+static const MemoryRegionOps bonito_cop_ops = {
+ .read = bonito_cop_readl,
+ .write = bonito_cop_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr)
@@ -710,14 +706,12 @@ static int bonito_initfn(PCIDevice *dev)
sysbus_init_mmio_region(sysbus, &s->iomem_ldma);
sysbus_mmio_map(sysbus, 3, 0xbfe00200);
- s->bonito_cop_handle = cpu_register_io_memory(bonito_cop_read,
- bonito_cop_write, s,
- DEVICE_NATIVE_ENDIAN);
- s->bonito_cop_start = 0xbfe00300;
- s->bonito_cop_length = 0x100;
- cpu_register_physical_memory(s->bonito_cop_start, s->bonito_cop_length,
- s->bonito_cop_handle);
+ memory_region_init_io(&s->iomem_cop, &bonito_cop_ops, s,
+ "cop", 0x100);
+ sysbus_init_mmio_region(sysbus, &s->iomem_cop);
+ sysbus_mmio_map(sysbus, 4, 0xbfe00300);
+ /* end */
/* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */
s->bonito_pciio_start = BONITO_PCIIO_BASE;
s->bonito_pciio_length = BONITO_PCIIO_SIZE;
--
1.7.7.3
^ permalink raw reply related [flat|nested] 13+ messages in thread