From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:59636) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RSx3p-0005Lc-Tl for qemu-devel@nongnu.org; Tue, 22 Nov 2011 15:35:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RSx3o-0004mG-7E for qemu-devel@nongnu.org; Tue, 22 Nov 2011 15:35:21 -0500 Received: from mail-fx0-f45.google.com ([209.85.161.45]:37913) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RSx3o-0004j5-03 for qemu-devel@nongnu.org; Tue, 22 Nov 2011 15:35:20 -0500 Received: by mail-fx0-f45.google.com with SMTP id s14so959036faa.4 for ; Tue, 22 Nov 2011 12:35:19 -0800 (PST) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= Date: Tue, 22 Nov 2011 21:35:00 +0100 Message-Id: <1321994102-28263-10-git-send-email-benoit.canet@gmail.com> In-Reply-To: <1321994102-28263-1-git-send-email-benoit.canet@gmail.com> References: <1321994102-28263-1-git-send-email-benoit.canet@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v3 09/11] bonito: convert south bridge pci config to memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Beno=C3=AEt=20Canet?= , avi@redhat.com Signed-off-by: Benoît Canet --- hw/bonito.c | 40 +++++++++++++++++++--------------------- 1 files changed, 19 insertions(+), 21 deletions(-) diff --git a/hw/bonito.c b/hw/bonito.c index 8fa709a..b4c3387 100644 --- a/hw/bonito.c +++ b/hw/bonito.c @@ -203,10 +203,7 @@ typedef struct PCIBonitoState /* Bonito registers */ MemoryRegion iomem; MemoryRegion iomem_pciconf; - - target_phys_addr_t bonito_spciconf_start; - target_phys_addr_t bonito_spciconf_length; - int bonito_spciconf_handle; + MemoryRegion iomem_spciconf; target_phys_addr_t bonito_pciio_start; target_phys_addr_t bonito_pciio_length; @@ -597,16 +594,20 @@ static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr) } /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */ -static CPUWriteMemoryFunc * const bonito_spciconf_write[] = { - bonito_spciconf_writeb, - bonito_spciconf_writew, - bonito_spciconf_writel, -}; - -static CPUReadMemoryFunc * const bonito_spciconf_read[] = { - bonito_spciconf_readb, - bonito_spciconf_readw, - bonito_spciconf_readl, +static const MemoryRegionOps bonito_spciconf_ops = { + .old_mmio = { + .read = { + bonito_spciconf_readb, + bonito_spciconf_readw, + bonito_spciconf_readl, + }, + .write = { + bonito_spciconf_writeb, + bonito_spciconf_writew, + bonito_spciconf_writel, + }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; #define BONITO_IRQ_BASE 32 @@ -703,13 +704,10 @@ static int bonito_initfn(PCIDevice *dev) sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE); /* set the south bridge pci configure mapping */ - s->bonito_spciconf_handle = cpu_register_io_memory(bonito_spciconf_read, - bonito_spciconf_write, s, - DEVICE_NATIVE_ENDIAN); - s->bonito_spciconf_start = BONITO_SPCICONFIG_BASE; - s->bonito_spciconf_length = BONITO_SPCICONFIG_SIZE; - cpu_register_physical_memory(s->bonito_spciconf_start, s->bonito_spciconf_length, - s->bonito_spciconf_handle); + memory_region_init_io(&s->iomem_spciconf, &bonito_spciconf_ops, s, + "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE); + sysbus_init_mmio_region(sysbus, &s->iomem_spciconf); + sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE); s->bonito_ldma_handle = cpu_register_io_memory(bonito_ldma_read, bonito_ldma_write, s, -- 1.7.7.3