From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:59609) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RSx3n-0005Dm-J5 for qemu-devel@nongnu.org; Tue, 22 Nov 2011 15:35:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RSx3m-0004lo-7e for qemu-devel@nongnu.org; Tue, 22 Nov 2011 15:35:19 -0500 Received: from mail-fx0-f45.google.com ([209.85.161.45]:37913) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RSx3l-0004j5-Mr for qemu-devel@nongnu.org; Tue, 22 Nov 2011 15:35:17 -0500 Received: by mail-fx0-f45.google.com with SMTP id s14so959036faa.4 for ; Tue, 22 Nov 2011 12:35:17 -0800 (PST) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= Date: Tue, 22 Nov 2011 21:34:58 +0100 Message-Id: <1321994102-28263-8-git-send-email-benoit.canet@gmail.com> In-Reply-To: <1321994102-28263-1-git-send-email-benoit.canet@gmail.com> References: <1321994102-28263-1-git-send-email-benoit.canet@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v3 07/11] bonito: convert north bridge register mapping to memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Beno=C3=AEt=20Canet?= , avi@redhat.com Signed-off-by: Benoît Canet --- hw/bonito.c | 39 ++++++++++++++++++--------------------- 1 files changed, 18 insertions(+), 21 deletions(-) diff --git a/hw/bonito.c b/hw/bonito.c index fdb8198..9260848 100644 --- a/hw/bonito.c +++ b/hw/bonito.c @@ -201,9 +201,7 @@ typedef struct PCIBonitoState } boncop; /* Bonito registers */ - target_phys_addr_t bonito_reg_start; - target_phys_addr_t bonito_reg_length; - int bonito_reg_handle; + MemoryRegion iomem; target_phys_addr_t bonito_pciconf_start; target_phys_addr_t bonito_pciconf_length; @@ -233,7 +231,8 @@ typedef struct PCIBonitoState PCIBonitoState * bonito_state; -static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void bonito_writel(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned size) { PCIBonitoState *s = opaque; uint32_t saddr; @@ -295,7 +294,8 @@ static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val) } } -static uint32_t bonito_readl(void *opaque, target_phys_addr_t addr) +static uint64_t bonito_readl(void *opaque, target_phys_addr_t addr, + unsigned size) { PCIBonitoState *s = opaque; uint32_t saddr; @@ -311,16 +311,14 @@ static uint32_t bonito_readl(void *opaque, target_phys_addr_t addr) } } -static CPUWriteMemoryFunc * const bonito_write[] = { - NULL, - NULL, - bonito_writel, -}; - -static CPUReadMemoryFunc * const bonito_read[] = { - NULL, - NULL, - bonito_readl, +static const MemoryRegionOps bonito_ops = { + .read = bonito_readl, + .write = bonito_writel, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, }; static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr, @@ -690,17 +688,16 @@ static int bonito_pcihost_initfn(SysBusDevice *dev) static int bonito_initfn(PCIDevice *dev) { PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev); + SysBusDevice *sysbus = sysbus_from_qdev(&dev->qdev); /* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */ pci_config_set_prog_interface(dev->config, 0x00); /* set the north bridge register mapping */ - s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s, - DEVICE_NATIVE_ENDIAN); - s->bonito_reg_start = BONITO_INTERNAL_REG_BASE; - s->bonito_reg_length = BONITO_INTERNAL_REG_SIZE; - cpu_register_physical_memory(s->bonito_reg_start, s->bonito_reg_length, - s->bonito_reg_handle); + memory_region_init_io(&s->iomem, &bonito_ops, s, + "north-bridge-register", BONITO_INTERNAL_REG_SIZE); + sysbus_init_mmio_region(sysbus, &s->iomem); + sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE); /* set the north bridge pci configure mapping */ s->bonito_pciconf_handle = cpu_register_io_memory(bonito_pciconf_read, -- 1.7.7.3