From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:59620) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RSx3o-0005HA-E5 for qemu-devel@nongnu.org; Tue, 22 Nov 2011 15:35:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RSx3n-0004m1-CR for qemu-devel@nongnu.org; Tue, 22 Nov 2011 15:35:20 -0500 Received: from mail-fx0-f45.google.com ([209.85.161.45]:37913) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RSx3m-0004j5-WF for qemu-devel@nongnu.org; Tue, 22 Nov 2011 15:35:19 -0500 Received: by mail-fx0-f45.google.com with SMTP id s14so959036faa.4 for ; Tue, 22 Nov 2011 12:35:18 -0800 (PST) From: =?UTF-8?q?Beno=C3=AEt=20Canet?= Date: Tue, 22 Nov 2011 21:34:59 +0100 Message-Id: <1321994102-28263-9-git-send-email-benoit.canet@gmail.com> In-Reply-To: <1321994102-28263-1-git-send-email-benoit.canet@gmail.com> References: <1321994102-28263-1-git-send-email-benoit.canet@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v3 08/11] bonito: convert north bridge pci config to memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Beno=C3=AEt=20Canet?= , avi@redhat.com Signed-off-by: Benoît Canet --- hw/bonito.c | 38 ++++++++++++++++---------------------- 1 files changed, 16 insertions(+), 22 deletions(-) diff --git a/hw/bonito.c b/hw/bonito.c index 9260848..8fa709a 100644 --- a/hw/bonito.c +++ b/hw/bonito.c @@ -202,10 +202,7 @@ typedef struct PCIBonitoState /* Bonito registers */ MemoryRegion iomem; - - target_phys_addr_t bonito_pciconf_start; - target_phys_addr_t bonito_pciconf_length; - int bonito_pciconf_handle; + MemoryRegion iomem_pciconf; target_phys_addr_t bonito_spciconf_start; target_phys_addr_t bonito_spciconf_length; @@ -322,7 +319,7 @@ static const MemoryRegionOps bonito_ops = { }; static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr, - uint32_t val) + uint64_t val, unsigned size) { PCIBonitoState *s = opaque; @@ -330,7 +327,8 @@ static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr, s->dev.config_write(&s->dev, addr, val, 4); } -static uint32_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr) +static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr, + unsigned size) { PCIBonitoState *s = opaque; @@ -340,16 +338,15 @@ static uint32_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr) } /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */ -static CPUWriteMemoryFunc * const bonito_pciconf_write[] = { - NULL, - NULL, - bonito_pciconf_writel, -}; -static CPUReadMemoryFunc * const bonito_pciconf_read[] = { - NULL, - NULL, - bonito_pciconf_readl, +static const MemoryRegionOps bonito_pciconf_ops = { + .read = bonito_pciconf_readl, + .write = bonito_pciconf_writel, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, }; static uint32_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr) @@ -700,13 +697,10 @@ static int bonito_initfn(PCIDevice *dev) sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE); /* set the north bridge pci configure mapping */ - s->bonito_pciconf_handle = cpu_register_io_memory(bonito_pciconf_read, - bonito_pciconf_write, s, - DEVICE_NATIVE_ENDIAN); - s->bonito_pciconf_start = BONITO_PCICONFIG_BASE; - s->bonito_pciconf_length = BONITO_PCICONFIG_SIZE; - cpu_register_physical_memory(s->bonito_pciconf_start, s->bonito_pciconf_length, - s->bonito_pciconf_handle); + memory_region_init_io(&s->iomem_pciconf, &bonito_pciconf_ops, s, + "north-bridge-pci-config", BONITO_PCICONFIG_SIZE); + sysbus_init_mmio_region(sysbus, &s->iomem_pciconf); + sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE); /* set the south bridge pci configure mapping */ s->bonito_spciconf_handle = cpu_register_io_memory(bonito_spciconf_read, -- 1.7.7.3